Driving capability and self-adjustment method and device of chip terminal resistance value
A technology of driving capability and terminating resistance, applied in electrical components, logic circuits, pulse technology, etc.
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[0043] figure 1 It is a system schematic diagram of a device for self-adjusting driving capability and chip terminal resistance according to an embodiment of the present invention. Please refer to figure 1 , in this embodiment, the device 100 for self-adjustment of drive capability and chip terminal resistance includes a system circuit 110, an output interface entity layer 120, a ring oscillator ROSC, a counter 130, a control unit 140, and a storage element 150, wherein the output interface For example, Universal Serial Bus (USB) 2.0, third-generation Double-Data-Rate Memory Three (DDR3) transmission interface or High Definition Multimedia (HDMI), etc. . The storage element 150 is used to store a reference count value CNTR, and may be a storage device such as an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory (FLASH Memory) or an electronic fuse (eFuse). element. The output interface physical layer 120 receives the operating voltage VOP, and is...
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