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Parallel test system and testing method thereof

A test system and wafer carrying technology, applied in the direction of semiconductor/solid-state device testing/measurement, single semiconductor device testing, etc., can solve problems such as body contact with moving knobs, wafer carrier plate movement, probe card damage, etc. achieve the effect of avoiding damage

Active Publication Date: 2014-10-01
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The present invention is aimed at the traditional parallel test system in the prior art, in the process of manual test, it is easy for the body to touch the moving knob, which will cause the wafer carrier to move, and then cause the probe card to move. damage, bring huge economic losses and other defects to provide a parallel testing system
[0007] Another purpose of the present invention is to address the traditional parallel test system in the prior art, during the manual test process, it is easy for the body to touch the moving knob, which will cause the wafer carrier to move, and then cause the The damage of the probe card mentioned above will bring huge economic losses and other defects to provide a test method for parallel test system

Method used

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  • Parallel test system and testing method thereof
  • Parallel test system and testing method thereof
  • Parallel test system and testing method thereof

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Embodiment Construction

[0019] In order to illustrate the technical content, structural features, achieved goals and effects of the present invention in detail, the following will be described in detail in conjunction with the embodiments and accompanying drawings.

[0020] see Figure 1 ~ Figure 3 , figure 1 Shown is a schematic structural diagram of the parallel testing system of the present invention. Figure 2(a) ~ Figure 2(b) Shown is a schematic structural diagram of the locking component of the parallel testing system of the present invention. image 3 Shown is a cross-sectional view of the parallel testing system of the present invention. The parallel test system 1 includes: a housing 10, the housing 10 encloses and forms an accommodating space 101, and the wafer carrying platform lifting knob 102 is arranged at intervals on the housing 10, and the wafer carrying platform moves left and right Knob 103, knob 104 for moving the wafer carrying platform back and forth; wafer carrying tray 11,...

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PUM

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Abstract

A parallel test system comprises a shell, a wafer bearing plate and a locking part. A containing space is defined in the shell, the shell is provided with a wafer bearing platform lifting knob, a wafer bearing platform left-right moving knob and a wafer bearing platform forward-backward moving knob at intervals, the wafer bearing plate is arranged in the containing space, the locking part further comprises locating pins and locking rings, the locating pins are arranged in a first through hole close to the wafer bearing platform left-right moving knob and in a second through hole close to the wafer bearing platform forward-backward moving knob respectively, and the locking rings are provided with locking holes at intervals and are fixedly arranged on a supporting plate under the first through hole and the second through hole. The locking part is arranged in the parallel test system, so that when the wafer bearing plate rises to a probe insertion height or an electric test height, the locating pins are inserted into the locking holes of the locking rings, the wafer bearing plate is prevented from moving again, and a probe clamp is prevented from being damaged.

Description

technical field [0001] The invention relates to the technical field of testing semiconductor devices, in particular to a parallel testing system and a testing method thereof. Background technique [0002] see Figure 4 , Figure 4 Shown is a schematic diagram of the structure of the existing parallel test system. The existing parallel test system 2 is a manual test machine, and the probe card 21 of the parallel test system 2 is fixedly arranged above the wafer carrier 23 through the probe card bracket 22 . During needle sticking or electrical testing, the test engineer will lift the wafer carrier 23 to a position adjacent to the probe card 21 through an operation performed by an external control key (not shown). [0003] However, because the parallel test system 2 is a manual test machine, the horizontal and vertical movement knobs (not shown) of the wafer carrier 23 are all facing the test engineer. The contact of the moving knob causes the wafer carrier tray 23 to move, ...

Claims

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Application Information

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IPC IPC(8): G01R31/26H01L21/66
Inventor 吴奇伟尹彬锋王炯
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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