Semiconductor memory device

A storage device and semiconductor technology, applied in information storage, static memory, digital memory information, etc., can solve problems such as increased power consumption, and achieve the effect of preventing malfunction

Active Publication Date: 2014-10-29
潘杰亚股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

An increase in leakage current in non-selected memory cells causes malfunction of the resistance change memory and increases power consumption

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0031]

[0032] figure 1 It is an example of a block diagram of the nonvolatile semiconductor memory device according to the first embodiment.

[0033] This nonvolatile semiconductor memory device includes a memory cell array 1 including a plurality of word lines WL, a plurality of bit lines BL intersecting the word lines WL, and a plurality of memory cell arrays provided on the word lines WL and bit lines BL. A plurality of memory cells MC at the intersection.

[0034] In the position adjacent to the bit line BL of the memory cell array 1, there is provided a memory cell that controls the bit line BL of the memory cell array 1 and performs data erasing, data writing, and self-storage of the memory cell MC. Column control circuit 2 for data readout of cell MC.

[0035] In addition, in the position adjacent to the word line WL direction of the memory cell array 1, there are provided the word line WL of the memory cell array 1 and the data erasing of the memory cell MC, the ...

no. 2 Embodiment approach

[0088] Next, referring to the semiconductor memory device according to the second embodiment Figure 10 Be explained. The configuration of the semiconductor memory device is basically the same as that of the first embodiment. In addition, it is also the same as the first embodiment in that the control circuit selects a memory cell, and after the set operation or reset operation is completed, the control circuit connects the bit lines BL and Memory cells MC different from both word lines WL are set as newly selected memory cells.

[0089] However, in the second embodiment, if Figure 10 As shown, it is different from the first embodiment in that the control circuit selects a bit line BL two away from the previous selected bit line BL, and selects a word line WL adjacent to the previous selected word line WL. This operation also provides the same effect as that of the first embodiment.

[0090] Also, by separating the selected memory cell from the previous selected memory ce...

no. 3 Embodiment approach

[0092] Next, referring to the semiconductor memory device according to the third embodiment Figure 11 Be explained. The configuration of the semiconductor memory device is basically the same as that of the first embodiment. In addition, it is the same as the first embodiment in that the control circuit selects a certain memory cell, and after the set operation or reset operation is completed, the control circuit connects the bit lines BL and Memory cells MC different from both word lines WL are set as newly selected memory cells.

[0093] However, in the third embodiment, if Figure 11 As shown, it differs from the first embodiment in that the control circuit sequentially selects memory cells in a so-called zigzag pattern with respect to the longitudinal direction of the bit line BL and the word line WL. Specifically, similarly to the first embodiment, the control circuit newly selects a memory cell located obliquely below the previously selected memory cell MC. After the...

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Abstract

This semiconductor memory device comprises: a memory cell array including plural bit lines, plural word lines intersecting the plurality of bit lines, and memory cells provided at intersections of the plural bit lines and the plural word lines; and a control unit operative to control a voltage applied to the bit line and the word line. The control unit, when performing a certain operation consecutively on a plurality of the memory cells, selects a first bit line selected from among the plural bit lines and a first word line selected from among the plural word lines to perform a first operation on a first memory cell. Then, in a subsequent second operation following this first operation, selects a second bit line different from the first bit line and a second word line different from the first word line to select a second memory cell.

Description

[0001] related application [0002] This application enjoys the priority of the basic application based on US Patent Provisional Application No. 61 / 815197 (filing date: April 23, 2013). This application incorporates the entire content of the basic application by referring to this basic application. technical field [0003] The embodiments described in this specification relate to semiconductor memory devices. Background technique [0004] In recent years, resistance change memory has attracted attention as a successor candidate of flash memory. A resistance change memory generally has a cross-point structure: at the intersections of a plurality of bit lines and a plurality of word lines crossing them, memory cells with variable resistance elements are arranged in a matrix. [0005] In such a cross-point type resistance change memory, a desired voltage is applied to a selected memory cell, and a current sufficient to change the resistance of the variable resistance element ...

Claims

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Application Information

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IPC IPC(8): G11C7/12G11C8/08G11C13/00
CPCG11C13/0026G11C13/0028G11C13/0002G11C2213/71G11C2213/72G11C2213/77
Inventor 曾根原岳志
Owner 潘杰亚股份有限公司
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