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Programmable amplified input signal amplitude SAR analog to digital converter and method thereof

一种输入信号、模拟数字的技术，应用在模数转换器、模/数转换、代码转换等方向，能够解决消耗芯片面积等问题，达到抑制电源噪声和共模噪声、噪声小的效果

Active Publication Date: 2014-10-29
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The existing technology mainly uses a programmable gain amplifier (programmable gain amplifier; PGA) to amplify the amplitude of the input signal, but the PGA itself consumes chip area and brings additional noise (noise)

Method used

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  • Programmable amplified input signal amplitude SAR analog to digital converter and method thereof
  • Programmable amplified input signal amplitude SAR analog to digital converter and method thereof
  • Programmable amplified input signal amplitude SAR analog to digital converter and method thereof

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Embodiment Construction

[0069] The following terms such as "first" and "second" are used to distinguish the referred elements, but not to sort or limit the difference of the referred elements, and are not used to limit the scope of the present invention.

[0070] refer to figure 1 , a progressive-approximation analog-to-digital converter 10 (successive-approximation-register analog-to-digital converter; SAR ADC) that can be programmed to amplify the amplitude of the input signal includes a first terminal N1, a second terminal N2, and a third terminal N3 , a fourth terminal N4 , a fifth terminal N5 , a comparator 110 , a SAR control circuit 130 , a selection module 170 and a capacitor module 150 .

[0071] The selection module 170 includes a plurality of switching units (hereinafter referred to as first switching units UA1, UA2-UA(N-1) and second switching units UB1, UB2-UB(N-1)) and two input switches (hereinafter referred to as They are the first switch SW1 and the second switch SW2). The capacito...

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Abstract

Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation.

Description

technical field [0001] The present invention relates to a progressive-approximation-register analog-to-digital converter (SAR ADC), in particular to a SAR ADC which can programmably amplify the amplitude of an input signal and a method thereof. Background technique [0002] Analog-to-digital converter (analog-to-digital converter; ADC) has a variety of architectures, such as: flash (flash) ADC, pipeline (pipelined) ADC, successive-approximation-register (SAR) ADC Wait. Each of these architectures has its own advantages and is usually selected based on different application requirements. Among them, SAR ADC consumes lower power, smaller area and lower cost than other architectures. [0003] The operation of SAR ADC begins with the sampling phase (sampling phase). During the sampling phase, the sample-and-hold circuit performs sample access to the analog input signal. Next, the SAR ADC enters the bit-cycling phase to determine the conversion output of the digital code. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/38
CPCH03M1/124H03M1/12H03M1/466H03M1/468
Inventor 杨军
Owner REALTEK SEMICON CORP