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All-unfolded-structured AES encryption/decryption circuit based on data redundancy real-time error detection mechanism

A data redundancy and data technology, applied in encryption devices with shift registers/memory, electrical components, error prevention, etc., can solve the problems of high data processing speed and large circuit area, so as to improve the effectiveness and reliability of information performance, avoiding wrong information transmission, and meeting the requirements of real-time data processing

Active Publication Date: 2014-11-19
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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Problems solved by technology

The fully expanded structure uses the N r +1 wheel conversion circuit unit, the circuit area is large, but the data does not need to be fed back, and the data processing speed is high

Method used

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  • All-unfolded-structured AES encryption/decryption circuit based on data redundancy real-time error detection mechanism
  • All-unfolded-structured AES encryption/decryption circuit based on data redundancy real-time error detection mechanism
  • All-unfolded-structured AES encryption/decryption circuit based on data redundancy real-time error detection mechanism

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Embodiment Construction

[0035] The present invention will be further described below with reference to the accompanying drawings and in conjunction with specific embodiments.

[0036] In the present invention, the round transformation operation that does not include column mixing (inverse column mixing) operation is called the last round of round transformation operation. The present invention also takes the key addition operation independent of the round transformation operation as a round of special round transformation operation. Since the reverse key addition operation is the same as the key addition operation, the present invention is collectively referred to as the key addition operation.

[0037] see image 3 , a fully expanded AES encryption / decryption circuit based on a data redundancy real-time error detection mechanism, comprising two parts of an AES encryption / decryption unit 1 and a detection unit 2, and the circuit also includes a data input port, a detection output port and a data out...

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Abstract

The invention discloses an all-unfolded-structured AES encryption / decryption circuit based on a data redundancy real-time error detection mechanism, and is used for resisting fault injection attacks or used for improving circuit reliability in an extreme application environment. The circuit comprises two parts of an AES encryption / decryption unit and a detecting unit, wherein the AES encryption / decryption unit adopts the all-unfolded structure, and is formed by a number Nr+2 of round transformation units and an alternative selector; the detecting unit is composed of a number Nr+1 of comparators. The AES encryption / decryption unit adopts the data redundancy processing technology in the data processing process, utilizes two adjacent round transformation units to perform the same operation on each group of data twice; the comparators in the detecting unit compare the results of the two operations; the AES encryption / decryption unit works normally if the operation results are the same; the AES encryption / decryption unit generates an error if the results are different. Compared with the conventional structural redundancy error detection mechanism, the adoption of data redundancy error detection mechanism can greatly reduce the circuit area.

Description

technical field [0001] The invention belongs to the technical field of cipher circuit realization, and in particular relates to an AES encryption / decryption circuit with a fully expanded structure based on a data redundancy real-time error detection mechanism. Background technique [0002] AES (Advanced Encryption Standard, Advanced Encryption Standard) is a new generation of block symmetric cipher algorithm formulated by the National Institute of Standards and Technology in 2001 to replace the original DES (Data Encryption Standard, Data Encryption Standard). The data packet length of the AES encryption algorithm is 128 bits, and there are three kinds of key lengths: 128, 192 and 256 bits. AES stipulates that according to these three different key lengths, the encryption process requires 10, 12, and 14 rounds of round transformation operations, and each round transformation operation includes byte replacement, row shifting, column mixing, and key addition. sub-operations, ...

Claims

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Application Information

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IPC IPC(8): H04L9/06H04L1/00
Inventor 张肖强吴宁陈鑫郑辛星李明星董礼玲
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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