AES encryption/decryption circuit based on data redundancy error detection mechanism

A data redundancy and data technology, applied in the direction of encryption device with shift register/memory, etc., can solve the problems of high data processing speed and large circuit area, so as to reduce circuit area, avoid wrong information transmission, and improve information efficiency. Effects of Sexuality and Reliability

Active Publication Date: 2014-11-19
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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  • Abstract
  • Description
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Problems solved by technology

The fully expanded structure uses the N r +1 wheel conversion circuit unit, the circuit area is large, but the data does not need to be fed back, and the data processing speed is high

Method used

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  • AES encryption/decryption circuit based on data redundancy error detection mechanism
  • AES encryption/decryption circuit based on data redundancy error detection mechanism
  • AES encryption/decryption circuit based on data redundancy error detection mechanism

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Embodiment Construction

[0043] The present invention will be further described below with reference to the accompanying drawings and in conjunction with specific embodiments.

[0044] In the present invention, the round transformation operation that does not include column mixing (inverse column mixing) operation is called the last round of round transformation operation. The present invention also takes the key addition operation independent of the round transformation operation as a round of special round transformation operation. Since the reverse key addition operation is the same as the key addition operation, the present invention is collectively referred to as the key addition operation.

[0045] see image 3 , an implementation example of the present invention is that the AES encryption / decryption unit adopts a fully expanded structure to realize. like image 3 As shown, the circuit structure includes AES encryption / decryption unit and comparator, and the circuit also includes data input p...

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Abstract

The invention discloses an AES encryption / decryption circuit based on a data redundancy error detection mechanism, and is used for resisting fault injection attacks or used for improving circuit reliability in an extreme application environment. The circuit comprises two parts of an AES encryption / decryption unit and a comparator, wherein the AES encryption / decryption unit is used for AES encryption / decryption operation; the AES encryption / decryption unit adopts the data redundancy processing technology in the data processing process, and utilizes two adjacent round transformation units to perform an identical operation on each group of data twice; the comparator in the detecting unit compares the results of the two operations; the AES encryption / decryption unit works normally if the operation results are the same, and the AES encryption / decryption unit generates an error if the operation results are different. Compared with a conventional structural redundancy error detection mechanism, the data redundancy error detection mechanism can greatly reduce circuit area.

Description

technical field [0001] The invention belongs to the technical field of cryptographic circuit realization, in particular to an AES encryption / decryption circuit based on a data redundancy error detection mechanism. Background technique [0002] AES (Advanced Encryption Standard, Advanced Encryption Standard) is a new generation of block symmetric cipher algorithm formulated by the National Institute of Standards and Technology in 2001 to replace the original DES (Data Encryption Standard, Data Encryption Standard). The data packet length of the AES encryption algorithm is 128 bits, and there are three kinds of key lengths: 128, 192 and 256 bits. AES stipulates that according to these three different key lengths, the encryption process requires 10, 12 and 14 rounds of round transformation operations, each round transformation operation includes byte replacement, row shift, column mixing and key addition. Four sub-operations, except the last round. In order to eliminate the s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/06
Inventor 吴宁张肖强葛芬叶云飞魏永康刘摇平
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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