FPGA-based process layer message filtering and bandwidth control method
A message filtering and bandwidth control technology, applied in digital transmission systems, electrical components, transmission systems, etc., can solve the problems of process layer network impact, device paralysis, etc., and achieve the effect of flexible functions, high integration, and reduced transmission load.
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[0028] The present invention will be further described below in conjunction with the accompanying drawings. The following examples are only used to illustrate the technical solution of the present invention more clearly, but not to limit the protection scope of the present invention.
[0029] according to figure 1 , after the process layer network is established, the multicast address of the Internet message is relatively stable, and the specified multicast address is filtered to reduce the actual number of messages that the processor needs to process. According to the IEEE 802.3 protocol, the destination address of an Ethernet packet is fixed at 6 bytes after the start character. After finding out the destination address from the message, compare it with the set destination address allowed to be received by looking up the table. The address that can be found in the table is the acceptable message, otherwise it is discarded. Only one of the packets with the same destination ...
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