Coherent light OFDM system receiving end high-speed data parallel processing structure and method

A coherent optical and data technology, applied in multi-frequency code systems, baseband system components, shaping networks in transmitters/receivers, etc. The effect of processing power

Active Publication Date: 2014-12-03
BEIJING UNIV OF POSTS & TELECOMM
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  • Claims
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Problems solved by technology

[0005] The purpose of the present invention is to solve the problem of high clock frequency a

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  • Coherent light OFDM system receiving end high-speed data parallel processing structure and method
  • Coherent light OFDM system receiving end high-speed data parallel processing structure and method
  • Coherent light OFDM system receiving end high-speed data parallel processing structure and method

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Embodiment 1

[0052] Below in conjunction with specific embodiment this patent is described in detail. Apply the DSP parallel processing structure and method at the receiving end of the coherent optical OFDM system proposed in this patent to the 480GbpsPM-16QAM-OFDM system. Figure 4 For the 480Gbps PM-16QAM-OFDM system adopts the structure of the present invention to carry out parallel processing of receiving end data, figure 2 It is a structure in which dual training symbols are used to perform parallel symbol synchronization and a judging mechanism for starting points of double-peak symbol synchronization in the embodiment. Figure 5 Algorithm flow adopted for the judging mechanism of the starting point of the double-peak symbol applied to the embodiment.

[0053] In this embodiment, the optimal number of parallel channels M is determined according to the requirements of dispersion compensation and the number of FFT points. M is 1024, the number of OFDM subcarriers N is 128, L=N / 2=64, ...

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Abstract

The invention discloses a coherent light OFDM system receiving end high-speed data parallel processing structure and method. The structure comprises a DC coarse equalization module, a parallel symbol synchronization module, a parallel FFT window module, a subsequent DSP processing module and a data recovery module. The method comprises the steps that firstly the characteristics of dispersion compensation are utilized so that a high-speed serial data flow string is converted into a parallel data flow string and then reduced to be within the processable range of a chip clock; then double training symbols are arranged and a double related peak decision mechanism is introduced so that symbol synchronization parallel processing is achieved and fractional frequency offset estimation and compensation functions are completed; and finally partitioning processing is performed on multipath parallel data. The requirement of a high-speed optical fiber communication system for ADC/DAC sampling rate and DSP algorithm chip processing speed is reduced by the structure and the method so that a problem that a DSP algorithm processing chip cannot meet the real-time processing requirement of the system is solved.

Description

technical field [0001] The present invention relates to high-speed optical fiber communication, especially to the field of DSP processing at the receiving end of high-speed optical fiber communication system, in particular to digital signal processing (Digital Signal Processing, Parallel implementation process of DSP processing (hereinafter referred to as DSP) background technology. Background technique [0002] In recent years, driven by "high-definition, three-dimensional, and user-created content", the generation of massive information has led to an alarming increase in network bandwidth. By 2016, global IP traffic will reach 1300 exabytes (1018) bytes per year. According to the data released by China Telecom, the compound annual growth rate of its network transmission bandwidth exceeds 80%, and the growth rate exceeds 10 times in five years. The improvement of single-channel transmission capacity can not only meet the requirements of rapid growth of transmission capaci...

Claims

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Application Information

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IPC IPC(8): H04L27/26H04L25/03
Inventor 陈雪闫峥刘耀超王邦醒王立芊张治国
Owner BEIJING UNIV OF POSTS & TELECOMM
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