Self-triggering stack stscr‑ldmos high voltage esd protection circuit

Abstract

The invention provides a high-voltage ESD protection circuit of self-triggering stacked STSCR-LDMOS, belonging to the technical field of electronics. It includes N STSCR-LDMOS stacking units, the STSCR-LDMOS stacking unit includes a STSCR-LDMOS device and a resistor, where N≥2, and there are N+1 P-type heavily doped regions on the substrate as guard rings to ground . The circuit breaks down and triggers the stacked STSCR-LDMOS through the first STSCR-LDMOS, effectively increasing the sustain voltage without increasing the trigger voltage.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to the design technology of an electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit chip, especially a self-triggering stacked STSCR-LDMOS (embedded with a laterally diffused metal oxide semiconductor field Effect transistor LDMOS Substrate-TriggerSilicon Controlled Rectifier, referred to as STSCR-LDMOS) high-voltage ESD protection circuit. Background technique [0002] During chip production, packaging, testing, storage, and handling, electrostatic discharge (ElectroStatic Discharge, ESD for short) exists as an inevitable natural phenomenon. With the reduction of the feature size of integrated circuit technology and the development of various advanced technologies, it is more and more common for chips to be damaged by ESD phenomena. Relevant research and investigations have shown that 30% of integrated circuit failure products are ...

AI Technical Summary

Problems solved by technology

However, if STSCR is used as a high-voltage ESD protection device, the very low maintenance voltage of STSCR will cause it to be prone to latch-up (latch-up) effect when it is used as a power supply clamp. After the ESD discharge is completed, the power supply continues to discharge and eventually burns out. bad device

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