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A high-voltage ESD protection circuit with stacked stscr‑ldmos

An ESD protection, high-voltage technology, applied in the electronic field, can solve the problems of burning out devices, low maintenance voltage, etc., and achieve the effect of reducing the risk of latch-up effect

Active Publication Date: 2017-05-10
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if STSCR is used as a high-voltage ESD protection device, the very low maintenance voltage of STSCR will cause it to be prone to latch-up (latch-up) effect when it is used as a power supply clamp. After the ESD discharge is completed, the power supply continues to discharge and eventually burns out. bad device

Method used

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  • A high-voltage ESD protection circuit with stacked stscr‑ldmos
  • A high-voltage ESD protection circuit with stacked stscr‑ldmos
  • A high-voltage ESD protection circuit with stacked stscr‑ldmos

Examples

Experimental program
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Effect test

Embodiment 1

[0038] image 3 The structural schematic diagram of the high-voltage ESD protection circuit of the LDMOS trigger stack STSCR-LDMOS provided in this embodiment includes a P-type substrate 201, a first high-voltage N-type well region 202, a second high-voltage N-type well region 203, and a third high-voltage N-type well region. type well region 204, the first P type well region 205, the second P type well region 206, the third P type well region 207, the first P type heavily doped region 208, the second P type heavily doped region 211, the second P type well region Three P-type heavily doped regions 212, fourth P-type heavily doped regions 214, fifth P-type heavily doped regions 215, sixth P-type heavily doped regions 217, seventh P-type heavily doped regions 218, Eight P-type heavily doped regions 220, ninth P-type heavily doped regions 221, tenth P-type heavily doped regions 223, eleventh P-type heavily doped regions 224, first N-type heavily doped regions 209, The second N-t...

Embodiment 2

[0052] Such as Figure 5 As shown, this embodiment uses PLDMOS instead of NLDMOS on the basis of Embodiment 1. At this time, the other end of the resistor 228 connected to the gate of PLDMOS is connected to the anode of STSCR-LDMOS1, and the rest of the connection methods are the same as those of NLDMOS , the working principle of this embodiment is the same as that of Embodiment 1.

[0053] Embodiment 2 uses PLDMOS instead of NLDMOS to trigger the stacked STSCR-LDMOS structure, because PLDMOS has a higher sustain voltage than NLDMOS, so that the sustain voltage after the first snapback is higher, so the anti-noise capability is stronger.

Embodiment 3

[0055] Such as Figure 8 As shown, this embodiment removes the resistor 230 on the basis of Embodiment 1. The working principle of this embodiment is the same as that of Embodiment 1.

[0056] Embodiment 3 removes the resistor 230, so that all the current after the NLDMOS breaks down flows through the resistor 304, which can increase the turn-on speed of the STSCR-LDMOS.

[0057] Figure 6 The equivalent circuit diagram of the high-voltage ESD protection circuit of the LDMOS trigger stacked STSCR-LDMOS provided by the present invention. The present invention can greatly increase the sustain voltage by stacking more STSCR-LDMOS stacked units 501, and more effectively prevent the occurrence of latch-up effect.

[0058] Figure 7 The I-V curve simulation diagram of NLDMOS triggering different stack numbers of STSCR-LDMOS is given, from Figure 7 It can be seen that, as the number of stacks increases, the breakdown voltage increases from 70V to 74.8V, while the sustain voltag...

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Abstract

The invention provides a high-voltage ESD protection circuit with stacked STSCR-LDMOS, which belongs to the field of electronic technology. Including 1 NLDMOS, 1 resistor 228 and N STSCR-LDMOS stacked units, the STSCR-LDMOS stacked unit includes a STSCR-LDMOS device and a trigger resistor, where N≥2, and (N+2 ) a P-type heavily doped region is grounded as a guard ring. The circuit triggers the stacked STSCR-LDMOS through the breakdown of the LDMOS, and uses the stacked STSCR to increase the sustain voltage without increasing the trigger voltage.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to an electrostatic discharge (ElectroStatic Discharge, referred to as ESD) protection circuit design technology for a semiconductor integrated circuit chip, especially a laterally diffused metal oxide semiconductor field effect transistor LDMOS (Laterally Diffused Metal Oxide Semiconductor, LDMOS for short) triggers the high-voltage ESD protection circuit of stacked STSCR-LDMOS (Substrate-Trigger Silicon Controlled Rectifier embedded with LDMOS, STSCR-LDMOS for short). Background technique [0002] During chip production, packaging, testing, storage, and handling, electrostatic discharge (ElectroStatic Discharge, ESD for short) exists as an inevitable natural phenomenon. With the reduction of the feature size of integrated circuit technology and the development of various advanced technologies, it is more and more common for chips to be damaged by ESD phenomena. Rel...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
Inventor 乔明马金荣张昕张晓菲张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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