Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders

A logarithmic likelihood ratio and damping technology, which is applied to the application of multi-bit parity bit error detection coding, coding, instruments, etc., can solve the problem of reducing the storage capacity of NVM

Active Publication Date: 2015-01-14
LSI CORPORATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

For example, by reducing the coding rate of the BCH code, the ECC is improved. However, reducing the coding rate will reduce the storage capacity of the NVM

Method used

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  • Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders
  • Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders
  • Log-likelihood ratio (LLR) dampening in low-density parity-check (LDPC) decoders

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Embodiment Construction

[0024] The described embodiments provide a media controller that reads data stored in the media. The media controller determines the value of each bit of the shortened codeword from the media. The shortened codeword comprises a plurality of non-shortened bits of a full codeword, wherein the full codeword comprises a plurality of non-shortened bits and one or more shortened bits. The shortened bits correspond to unused bits in the shortened codeword. The media controller converts the determined value of each bit of the shortened codeword into a first set of log-likelihood ratio (LLR) values. The full codeword is decoded using the first set of LLR values ​​of the shortened codeword. The media controller dampens one or more LLR values ​​corresponding to the non-shortened bits of the codeword to generate a second set of LLR values, and decodes the second set of LLR values.

[0025] Table 1 defines a list of acronyms used throughout this specification to aid in understanding the...

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Abstract

Described embodiments provide a media controller to read data stored in a media. The media controller determines a value for each bit of a shortened codeword from the media. The shortened LDPC codeword includes a plurality of non-shortened bits of a full codeword, where the full codeword includes the plurality of non-shortened bits and one or more shortened bits. Shortened bits correspond to bits unused in the shortened codeword. The media controller converts the determined values for each bit of the shortened codeword into a first set of log-likelihood ratio (LLR) values. The full codeword is decoded using the first set of LLR values for the shortened codeword. If the LDPC decoding fails, the media controller dampens one or more LLR values corresponding to non-shortened bits of the codeword to produce a second set of LLR values and starts a second LDPC decoding trial using the second set of LLR values. The dampening of LLR values includes scaling by a predetermined scaling factor and decreasing their magnitude by a predetermined amount.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of the filing date of US Provisional Patent Application 61 / 729,178, filed November 21, 2012, which is incorporated herein by reference in its entirety. [0003] The subject matter of this application is related to US Patent Applications 13 / 464,433, filed May 4, 2012, and 13 / 567,025, filed August 4, 2012, which are incorporated herein by reference in their entirety. Background technique [0004] Flash memory is non-volatile memory (NVM), which is a specific type of electrically erasable programmable read-only memory (EEPROM). One commonly used type of flash memory technology is NAND flash memory. NAND flash memory requires a small chip area per cell, usually divided into one or more memory banks or planes. Each memory bank is divided into blocks; each block is divided into pages. Each page consists of several bytes used to store user data, error correction code (ECC) information, or ...

Claims

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Application Information

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IPC IPC(8): H03M13/11
CPCH03M13/1142H03M13/1111H03M13/6591H03M13/3723H03M13/618H03M13/6306H03M13/658G06F11/1012
Inventor E·T·科恩E·F·哈拉特施A-H·S·埃侯赛因
Owner LSI CORPORATION
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