Flexibly configured programmable system-on-chip chip and starting configuration method thereof

Abstract

The invention discloses a flexibly configured programmable system-on-chip chip and a starting configuration method thereof. The chip comprises a kernel module, an on-chip bus, a starting configuration module, a system control module, a storage control module, a floating-point calculation speed-up module, a direct memory access (DMA) control module, a universal external port control module, an embedded storage module and an embedded field programmable gate array (FPGA). By means of the flexibly configured programmable system-on-chip chip and the starting configuration method thereof, various configurations of the FPGA can be achieved through the embedded storage module or an external storer, and diversification of FPGA configuration modes can be effectively improved; by means of any external arrangement of a universal port mounted on bus resources, flexible configuration of the FPGA can be finished, and problems that single configuration mode exists and object-oriented configuration according to practical application cannot be achieved can be effectively solved; after starting of the kernel module, FPGA configuration modes can be guided, the FPGA configuration process can be controlled, and the controllability of the configuration process can be effectively improved; the flexibly configured programmable system-on-chip chip and the starting configuration method thereof are widely applicable to the field of integrated circuits.

Description

Technical field

[0001] The present invention relates to the technical field of integrated circuits, in particular to a programmable system-on-chip chip that can be flexibly configured and a startup configuration method thereof. Background technique

[0002] With the development of microelectronics technology, SOC has become the focus of the IC design industry. SOC performance is getting stronger and stronger, and the scale is getting bigger and bigger. The scale of SOC chips is generally much larger than that of ordinary ASICs. At the same time, the complexity of SOC design is greatly increased due to design difficulties caused by deep sub-micron processes. In particular, for some SOCs that are only used in small batches or are out of the development stage, if they are put into tape-out production immediately, they need to invest a lot of money and bear a greater risk of trial production. SOPC (System on a Programmable Chip) technology provides an effective solution.

[0003] Co...

Examples

Embodiment 1

[0049] Embodiment 1. In this embodiment, the chip core startup data is stored in an embedded storage module. In this embodiment, the embedded storage module is an SPI Flash chip. The FPGA configuration data is stored in an external memory. The external memory is a NOR Flash chip in this embodiment.

[0050] S11. The boot configuration module first moves the kernel boot data from the SPI Flash chip to the memory of the chip kernel module, and the memory is a high-speed cache integrated by the kernel. After the data transfer is completed, the chip kernel fetches instructions from the memory to execute the power-on startup program;

[0051] S12. After the kernel module completes the startup, the kernel module will notify the startup configuration module that the FPGA configuration data is stored in an external memory, and the external memory is a NOR Flash chip in this embodiment. At the same time, the kernel module will also configure the offset address of the FPGA configuration dat...

Embodiment 2

[0053] Embodiment 2. In this embodiment, the chip core startup data is stored in an external memory. The external memory is a NAND Flash chip in this embodiment, and the FPGA configuration data is stored on an on-chip bus controlled by the universal peripheral interface control module. On the mounted related interface peripherals, the external memory in this embodiment is an SPI Flash controlled by an SPI controller.

[0054] S21. The boot configuration module first moves the core boot data from the NAND Flash chip through the on-chip bus to the memory of the chip core module, where the memory is a high-speed cache integrated by the core. After the data transfer is completed, the chip kernel fetches instructions from the memory to execute the power-on startup program;

[0055] S22. After the kernel finishes booting, the kernel module will notify the boot configuration module, and the FPGA configuration data is stored in the peripheral controlled by the general peripheral interface ...

Technical field

[0001] The present invention relates to the technical field of integrated circuits, in particular to a programmable system-on-chip chip that can be flexibly configured and a startup configuration method thereof. Background technique

[0002] With the development of microelectronics technology, SOC has become the focus of the IC design industry. SOC performance is getting stronger and stronger, and the scale is getting bigger and bigger. The scale of SOC chips is generally much larger than that of ordinary ASICs. At the same time, the complexity of SOC design is greatly increased due to design difficulties caused by deep sub-micron processes. In particular, for some SOCs that are only used in small batches or are out of the development stage, if they are put into tape-out production immediately, they need to invest a lot of money and bear a greater risk of trial production. SOPC (System on a Programmable Chip) technology provides an effective solution.

[0003] Co...

Examples

Embodiment 1

[0049] Embodiment 1. In this embodiment, the chip core startup data is stored in an embedded storage module. In this embodiment, the embedded storage module is an SPI Flash chip. The FPGA configuration data is stored in an external memory. The external memory is a NOR Flash chip in this embodiment.

[0050] S11. The boot configuration module first moves the kernel boot data from the SPI Flash chip to the memory of the chip kernel module, and the memory is a high-speed cache integrated by the kernel. After the data transfer is completed, the chip kernel fetches instructions from the memory to execute the power-on startup program;

[0051] S12. After the kernel module completes the startup, the kernel module will notify the startup configuration module that the FPGA configuration data is stored in an external memory, and the external memory is a NOR Flash chip in this embodiment. At the same time, the kernel module will also configure the offset address of the FPGA configuration dat...

Embodiment 2

[0053] Embodiment 2. In this embodiment, the chip core startup data is stored in an external memory. The external memory is a NAND Flash chip in this embodiment, and the FPGA configuration data is stored on an on-chip bus controlled by the universal peripheral interface control module. On the mounted related interface peripherals, the external memory in this embodiment is an SPI Flash controlled by an SPI controller.

[0054] S21. The boot configuration module first moves the core boot data from the NAND Flash chip through the on-chip bus to the memory of the chip core module, where the memory is a high-speed cache integrated by the core. After the data transfer is completed, the chip kernel fetches instructions from the memory to execute the power-on startup program;

[0055] S22. After the kernel finishes booting, the kernel module will notify the boot configuration module, and the FPGA configuration data is stored in the peripheral controlled by the general peripheral interface ...

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