Bus arbitration method and device

Abstract

Disclosed is a bus arbitration method, comprising: in accordance with arbitration criteria, engaging in the arbitration of a presently received, and sent by an external device, bus access request and / or previously-stored bus access request, and storing the arbitration results; executing the stored arbitration results, and sending a corresponding arbitration response signal to the external device from which the bus access request and / or previously-stored bus access request are presently sent. Additionally disclosed is a bus arbitration device and a storage medium. Said method and device increase the transmission efficiency and circuit frequency of a bus, can satisfy high-speed interconnectivity requirements, and can be used in chips having relatively high bus throughput rates.

Description

technical field [0001] The invention relates to processor arbitration technology in the field of chips, in particular to a bus arbitration method and device. Background technique [0002] At present, arbitration is divided into two categories: centralized arbitration and distributed arbitration. Among them, distributed arbitration has good scalability, but the arbitration efficiency is low; the independent request method in centralized arbitration has high arbitration efficiency and can be completed in one clock cycle. One request arbitration, this independent request method is suitable as the bus arbitration method inside the chip. [0003] In order to efficiently respond to external requests, the common implementation scheme of the bus arbitration unit based on the independent request method is: in a certain clock cycle, the arbitration unit receives the request of each active module on the bus, according to the configurable priority or fixed priority or After arbitration...

AI Technical Summary

Problems solved by technology

[0004] figure 1 It is a timing diagram of the general arbitration implementation scheme in the prior art. Although the arbitration efficiency of the general arbitration implementation scheme in the prior art is high, there is a long delay when the grant signal returned to the active module passes through the arbitration logic, and the processor In the design, the grant signal will also control the root clock switch of the entire pipeline. Since the leaf clock used by the circuit is behind the root clock, the timing requirements are stricter, so this kind of scheme is not suitable for high-speed interconnect design, processor design and request module. Designs with multiple requests and long delays in arbitration

[0005] figure 2 It is a block diagram of an improved arbitration implementation scheme in the prior art, and it is an improvement scheme to a general arbitration implementation scheme. By using a register to tap the grant signal, the tapped grant signal is output to the active module, thereby supporting high-speed interconnection , support the processor switch clock, and support a large number of active modules; however, this solution requires two clock cycles to complete a request transmission, and the transmission efficiency is low

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