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Method for manufacturing packaging assembly

A technology for packaging components and packaging materials, which is applied in semiconductor/solid-state device manufacturing, electrical components, and electrical solid-state devices, etc., and can solve problems such as increased cost and complex manufacturing process of multi-layer packaging components.

Active Publication Date: 2015-03-11
SILERGY SEMICON TECH (HANGZHOU) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In view of this, the object of the present invention is to provide a method for manufacturing packaged components to solve the problem of increased cost due to the complexity of the manufacturing process of multilayer packaged components

Method used

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  • Method for manufacturing packaging assembly
  • Method for manufacturing packaging assembly

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Embodiment Construction

[0032] Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. For simplicity, the package structure obtained after several steps can be described in one figure.

[0033] It should be understood that when describing a package structure, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may refer to being directly on another layer or another region, or on There are other layers or regions between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region. If it is to describe the situation directly on another layer or another area, the expression "directly on" or "on and adjacent to" ...

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Abstract

Disclosed in the invention is a method for manufacturing a packaging assembly. The method comprises the following steps that: a lead frame is formed at a substrate, wherein the lead frame includes a plurality of leads and first surfaces of the leads are exposed; electronic elements at a plurality of levels are installed at the lead frame, so that the electronic elements at at least one level are electrically connected with the first surfaces of at least one group of leads among the multiple leads; and at least one part of the substrate is removed, so that second surfaces, opposite to the first surface, of the multiple leads are exposed for external connection. According to the method, overturning of a semiconductor structure during the manufacturing process is not needed. The yield of the packaging assemblies can be improved; the cost can be lowered; and the packaging quality can be enhanced.

Description

technical field [0001] The present invention relates to semiconductor packaging, and in particular to a method of manufacturing a packaging assembly. Background technique [0002] With the increasing demand for miniaturization, light weight and multi-functionalization of electronic components, the requirements for semiconductor packaging density are getting higher and higher, so as to achieve the effect of reducing the package size. Therefore, a package assembly using a lead frame and containing multiple semiconductor dies has become a new hot spot. In such packages, the configuration of the plurality of semiconductor dies and their connection methods have a critical impact on the size and performance of the package. [0003] Stacked multilayer package assemblies have been proposed in which multiple semiconductor dies are stacked on the same lead frame. The lowermost semiconductor die can be directly attached to the lead frame by solder. The semiconductor die on the upper...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L21/58
CPCH01L2224/16
Inventor 谭小春申屠军立叶佳明
Owner SILERGY SEMICON TECH (HANGZHOU) CO LTD
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