Efficient clock input control circuit

Abstract

The invention relates to an efficient clock input control circuit. The circuit comprises an external clock signal end CLK, wherein the external clock signal end CLK is connected with and controls grids of an NMOS transistor MN2 and an NMOS transistor MN1 which are connected in series respectively through a PATH1 channel and a PATH2 channel, the external clock signal end CLK is directly connected to the grid of the NMOS transistor MN1 through the PATH2 channel, an internal clock ACT signal feedback circuit is arranged in the PATH1 channel, CKII and CLK signals are generated to control the NMOS transistor MN2 and the NMOS transistor MN1 together, and the ACT signal feedback circuit mainly comprises a three-input NAND gate NAND and a two-input NOR gate NOR. According to the efficient clock input control circuit, reliable memory internal control clocks can be generated under different input clock conditions, particularly when clock rising / falling time is longer; the circuit is high in efficiency and high in reliability.

Description

technical field [0001] The invention belongs to the field of integrated circuits and memories, in particular to an efficient clock input control circuit with a clock ACT signal feedback loop. Background technique [0002] With the continuous improvement of integrated circuit design level and process technology, the complexity of the circuit has also increased. Today's designed chips range from a few million gates to tens of millions of gates. At the same time, there is an increasing demand for high speed and low power consumption of complex circuits, especially in processors, memories, personal computers and computer systems. According to statistics, memory has accounted for 22% of the total integrated circuit market in 2010. Coupled with the continuous introduction of advanced technology in recent years, the proportion of memory in the entire market has expanded. [0003] In order to improve the performance of complex circuit systems, it has become a trend to integrate a s...

AI Technical Summary

Problems solved by technology

[0007] In high-speed applications, follow the figure 1 In the memory clock input control circuit, if the rise / fall time of the external input clock is large, the traditional circuit cannot fully meet the requirements

In this case, the CLK and CKII signals cannot be high at the same time, so the internal clock signal ACT may not be generated, causing the memory to fail to work, such as figure 2 shown

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