A verification method and device

Abstract

The embodiment of the present invention discloses a verification method, including: inputting a first excitation signal to the SoC through a first verification code, and the SoC performs a simulation operation on the first excitation signal to obtain the first value of the signal output by the SoC. A signal pattern; when the similarity between the first signal pattern and the pre-acquired signal pattern is less than a similarity threshold, generating a signal for assigning the first excitation signal to the first signal according to the first signal pattern Reconstructing the SoC of the graph; modifying the first verification code according to the difference between the first signal image and the pre-acquired signal graph to obtain a second verification code; inputting a second stimulus to the reconstruction SoC through the second verification code signal, the reconstruction SoC performs value processing on the second excitation signal to obtain a second signal pattern. Correspondingly, the embodiment of the present invention also discloses a verification device. The embodiments of the present invention can improve verification efficiency.

Description

technical field [0001] The invention relates to the communication field, in particular to a verification method and device. Background technique [0002] Simulation is currently widely used in the field of research and development, for example: Electronic Design Automation (EDA) simulation debugging is widely used in the fields of electricity and communication, and many invention designs require EDA simulation. Among them, in the EDA simulation, it is necessary to repeat the verification code system-on-chip (Systemona ChipSoC) many times. In practical applications, the SoC in a design is very large, and some even need to take up tens of gigabytes of hard disk space, and tens of gigabytes of memory are also needed in the verification process, and each verification takes a lot of time. It can be done for a long time. It can be seen that in the process of repeatedly verifying the SoC through verification codes or verifying the SoC through different verification codes, it take...

AI Technical Summary

Problems solved by technology

In practical applications, the SoC in a design is very large, and some even need to take up tens of gigabytes of hard disk space, and tens of gigabytes of memory are also needed in the verification process, and each verification takes a lot of time. long time can be done

It can be seen that in the process of repeatedly verifying the SoC through the verification code, or verifying the SoC through different verification codes, the time consumed is very long, and the resources of the simulation device are also very large.

In summary, the verification efficiency of the current verification method is relatively low

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