Semiconductor package

Abstract

A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

Description

【Technical field】 [0001] The present invention relates to semiconductor packages, and more particularly to a flip-chip semiconductor package with fan-out copper pillar bumps. 【Background technique】 [0002] As is known in the art, there are various (e.g., ball grid array (BGA), wire bonding, flip-chip, etc.) Bonds on both substrates mount the die on the substrates. In order to ensure miniaturization and multifunctionality of electronic products or communication devices, small semiconductor packages, multi-pin connections, high speed, and high functionality are required. [0003] The increase in the number of input-output (I / O) pins coupled with the increased demand for high-performance integrated circuits has led to the development of flip-chip packaging. Flip-chip technology uses bumps on the bonding pads of the chip for direct interconnection to the packaging medium. The chip is bonded face down to the packaging medium by the shortest path. This technology can be appli...

AI Technical Summary

Problems solved by technology

Even in the future wafer shrinkage will exceed that of bump pitch solutions on substrate carriers

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