Cross clock domain synchronizer internal constant testing circuit and method

Abstract

The invention relates to a cross clock domain synchronizer internal constant testing circuit and method. The testing circuit comprises an asynchronous data unit, a unit to be detected, a first metastable state counting unit, a second metastable state counting unit, a model selecting unit and a timing unit. The invention discloses the cross clock domain synchronizer internal constant testing circuit and method which are used when MTBF evaluation is conducted on a cross clock domain synchronizer. The content of the design and achieving of the domain synchronizer internal constant testing circuit, testing operation and data calculation is included in the cross clock domain synchronizer internal constant testing circuit and method. The cross clock domain synchronizer internal constant testing circuit and method solve the problem that the internal constant of the synchronizer is difficult to obtain accurately when the MTBF evaluation is conducted on the cross clock domain synchronizer, and can be applied to the synchronizer which is formed by registers different in technological parameter of main latches and auxiliary latches, and the reliability of testing results of the internal constant of the synchronizer is improved.

Description

technical field [0001] The invention belongs to the field of electronic technology, in particular to a circuit and method for testing internal constants of a cross-clock domain synchronizer. Background technique [0002] With the increase of electronic hardware design scale and the appearance of System On Chip (SOC, System On Chip), the cross-clock The number of domain signal circuits also increases accordingly, resulting in an increase in the probability of metastability caused by crossing clock domains in the circuit. Therefore, synchronous circuits composed of two registers cascaded or more registers cascaded are widely used, such as figure 1 As shown, this paper refers to the circuit as a synchronizer. However, the continuous progress of FPGA and ASIC technology has a negative impact on the solution of the metastable state, which greatly deteriorates the performance of the existing synchronizer. The increase of cross-clock domain signals in the same design and the red...

AI Technical Summary

Problems solved by technology

If the process parameters of the master latch and the slave latch of this register are different, use C 2M value instead of C 2 It will lead to inaccurate test results of internal constants of the synchronizer, thus affecting the accuracy of the synchronizer MTBF evaluation

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