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Method for improving semiconductor metal overlay alignment measurement mark

An alignment mark and semiconductor technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the inaccurate measurement results of metal-level alignment, abnormal mark morphology, and increased production costs. and other problems, so as to avoid the measurement results exceeding the range, reduce lithography rework, and improve the quality.

Inactive Publication Date: 2015-04-29
CSMC TECH FAB2 CO LTD
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Problems solved by technology

[0003] The disadvantage of the current level alignment measurement mark design for the current layer of metal alignment before the layer is that it is easy to cause the problem of abnormal mark shape
Because the outer ring groove of the front layer is a narrow groove, it is easy to embed small particles in the subsequent chemical mechanical polishing (CMP) step and affect the quality of the mark, which directly leads to inaccurate measurement results of the metal level alignment. Accurate or even beyond the specified range, bringing additional photolithography rework and increasing production costs

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  • Method for improving semiconductor metal overlay alignment measurement mark
  • Method for improving semiconductor metal overlay alignment measurement mark
  • Method for improving semiconductor metal overlay alignment measurement mark

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[0019] In order to make the above objects, features and advantages of the present invention more comprehensible, the specific implementation of the present invention will be described in detail below in conjunction with specific examples.

[0020] In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

[0021] Second, "one embodiment" or "an embodiment" referred to herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. "In one embodiment" appearing in different places in this specification does not all refer to the same embodime...

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Abstract

The invention discloses a method for improving a semiconductor metal overlay alignment measurement mark. The method comprises the following steps: generating a test mark which is designed corresponding to the alignment mark on a first main area of a current layer of a semiconductor device, wherein the test mark is generated according to a test pattern; generating a front-layer alignment mark, which is designed corresponding to the alignment mark, on the first main area of the front layer of the semiconductor device, the alignment mark is obtained according to a front-layer alignment pattern, and the front-layer alignment pattern is one that extrudes outwards from the first main area of the front layer and corresponds to the test pattern; evaluating and comparing the displacement deviation of the alignment mark based on the test mark; treating the front-layer alignment mark corresponding to the alignment mark with the minimum displacement deviation as an alignment reference for a next generating layer of the semiconductor device. The method provided by the invention can significantly improve the quality of the metal overlay alignment measurement mark, thereby ensuring the precision of the online metal overlay alignment measurement, preventing the phenomenon that the measurement result is out of scope due to abnormal metal overlay mark morphology, and reducing unnecessary photoetching rework.

Description

technical field [0001] The invention relates to metal overlay technology in semiconductor technology. Background technique [0002] The current metal level alignment measurement and marking process generally adopts the bar pattern alignment (bar in bar) design: the outer bar pattern is the front layer groove pattern, and the outer layer bar pattern is opened to become a groove through the front layer , the inner strip pattern is the strip area of ​​the metal space of the current layer, that is, the blank concave area formed after the metal photoresist is developed. By calculating the offset of the center of the bar pattern in the metal space relative to the center of the bar pattern passing through the previous layer, the measurement result of the metal layer of the current layer is aligned with the previous layer. [0003] The disadvantage of the current layer alignment measurement mark design for the current layer of metal alignment before the layer is that it is easy to ...

Claims

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Application Information

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IPC IPC(8): H01L23/544H01L21/02
Inventor 杜鹏许宗能李健鲍东兴
Owner CSMC TECH FAB2 CO LTD