High-speed low-power-consumption multi-threshold double-edge-trigger D-type flip-flop

Abstract

The invention discloses a high-speed low-power-consumption multi-threshold double-edge-trigger D-type flip-flop. The high-speed low-power-consumption multi-threshold double-edge-trigger D-type flip-flop comprises a low-power-consumption control circuit, a positive-edge trigger latch, a negative-edge trigger latch and a low-power-consumption output control circuit, wherein the low-power-consumption control circuit is used for receiving low-power-consumption control input signals slp and outputting signals sleep and nsleep respectively after buffering the low-power-consumption control input signals slp; the positive-edge trigger latch is used for receiving data signals d, normal-phase clock input signals clk, inverse-phase clock input signals nclk and the signals sleep and nsleep; the positive-edge trigger latch outputs signals qtp after latching the data signals d; the negative-edge trigger latch is used for receiving the data signals d, the normal-phase clock input signals clk, the inverse-phase clock input signals nclk and the signals sleep and nsleep and outputs giansl qtn after latching the data signals d; the low-power-consumption output control circuit is used for selecting values outputted by the positive-edge trigger latch or the negative-edge trigger latch. The high-speed low-power-consumption multi-threshold double-edge-trigger D-type flip-flop has the advantages of simple structure, transmission efficiency can be improved, static leakage current and power consumption can be reduced and the like.

Description

technical field [0001] The invention mainly relates to the field of large-scale integrated circuit design, in particular to a high-speed, low-power consumption multi-threshold double-edge trigger D-type flip-flop. Background technique [0002] With the continuous improvement of process technology, VLSI design has entered the deep submicron stage. The reduction of the feature size will inevitably lead to the decrease of the threshold voltage of the MOS device, so that the leakage current of the circuit increases exponentially with the reduction of the feature size, which directly causes the rapid increase of the leakage current power consumption of the circuit. Static power consumption caused by leakage current cannot be ignored. [0003] For systems operating in the GHz range, the power consumption reaches tens of watts, or even hundreds of watts. Excessive power consumption has brought a series of problems and has become an important obstacle to the development of VLSI. ...

AI Technical Summary

Problems solved by technology

Although it can reduce a certain power consumption, the tube itself will consume a certain amount of energy, and will increase the area of ​​the circuit and increase the complexity of the circuit design.

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