A test method and reference model device for hardware computing components to be tested
A computing component and reference model technology, applied in software testing/debugging, computing, special data processing applications, etc., can solve the problem of low efficiency and achieve the effect of reducing the amount of verification, simple verification, correctness and reliability assurance
Active Publication Date: 2018-07-03
BEIJING SMART LOGIC TECH CO LTD
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Problems solved by technology
In the simulation verification method, the focus is on how to efficiently discover behaviors that do not conform to the design specifications. Manual error checking is only applicable to a very small amount of data, and the efficiency is not high. Designers may use it when initially completing the code of the hardware computing unit to be tested. ;Automated verification platform is the guarantee of large data volume verification
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[0029] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
[0030] When designing a floating-point multiplier multiplexed with single and double precision, according to the IEEE 754 standard rounding method, the floating-point multiplication operation is directly written in the System Verilog language, and the rounding mode control cannot be directly performed in the high-level description, that is, assuming A, B and C are three double-precision floating-point numbers. When writing the C=A*B statement in System Verilog, the rounding method cannot be controlled. If a lower level is used, such as bit-by-bit description, the complexity of the reference model will be greatly increased, and the workload of verifying its correctness is no less than that of verifying the correctness of th...
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The invention discloses a testing method and a reference model device of a hardware computing component to be tested. The reference model device includes: an instruction decoding module, which is used to decode input instructions; a special data processing module, which processes special data operations according to the decoding result; a normal data processing module, which according to the decoding result, Process the normal data operation by calling the calculation module; the calculation module executes the corresponding operation by calling the hardware platform resources, and returns the operation result to the normal data processing module; the pipeline control module is used to realize the pipeline level control; the output module , used to output the results obtained by the special data processing module and the normal data processing module. The present invention deeply studies the characteristics of computing components, skillfully combines System Verilog and C language, fully utilizes the advantages of these two languages, and quickly and efficiently establishes the required reference model.
Description
technical field [0001] The invention belongs to the technical field of verification in integrated circuits, and in particular relates to the design of reference models of computing components. Background technique [0002] With the continuous improvement of the chip manufacturing process, the chip feature size has entered the era of ultra-deep submicron. At present, the typical value of the most advanced process that the foundry can provide is around 28nm. The scale of digital integrated circuits is getting larger and higher, the degree of integration is getting higher and higher, and the internal space states are becoming more and more complex. The result of this situation is that the probability of chip function and logic errors is greatly increased. In order to ensure the correctness of chip design and the reusability of IP, verification plays a key role. Judging from the technical information released by international advanced chip companies such as International Busin...
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IPC IPC(8): G06F17/50G06F11/36
Inventor 肖偌舟王惠娟林玻刘檬张志伟
Owner BEIJING SMART LOGIC TECH CO LTD