Three-dimensional stacked semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a three-dimensional stacked semiconductor structure and a manufacturing method thereof. The three-dimensional stacked semiconductor structure includes: a plurality of stacked layers formed on a substrate, at least one contact hole vertically formed in one of the stacked layers, a Conductors are formed in the contact holes, and a charge trapping layer is formed at least at sidewalls of these stacked layers. One of the laminations includes a multi-layer pillar body, which is formed by alternately stacking multiple insulating layers and multiple conductive layers, and a dielectric layer is formed on the multi-layer pillar body. Contact holes pass through the corresponding stacked dielectric layers, the insulating layers and the conductive layers. Conductors in the contact holes connect the conductive layers of the corresponding stack. Wherein, the upper surface of the conductor is higher than the upper surface of the corresponding stacked multi-layer pillars.

Description

technical field [0001] The present invention relates to a three-dimensional stacked semiconductor structure and its manufacturing method, and more particularly to a three-dimensional stacked semiconductor structure with a conductive strip connecting source contacts and its manufacturing method. Background technique [0002] A great feature of non-volatile memory element design is the ability to preserve the integrity of the data state when the memory element loses or removes power. Currently, many different types of non-volatile memory devices have been proposed in the industry. However, related companies are still developing new designs or combining existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some three-dimensional stacked NAND gate (NAND) flash memory structures have been proposed. However, there are still some problems to be solved in the conventional 3D stacked memory structure. [0003] f...

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Problems solved by technology

Furthermore, the source contact and the bit line of the traditional stacked structure are built on the same level, which will increase the difficulty of alignment between the source contact and the upper conductive plug when receiving the source contact process.

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