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Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as low impact resistance, low chip flexural strength, and longer cutting time, and achieve high productivity effect

Active Publication Date: 2015-05-20
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, there is a problem in blade dicing that if the chip size is reduced and the number of dicing grooves (number of lines) is increased, the dicing time becomes longer in proportion to the number of lines.
[0004] In addition, the corners of the chip obtained by cutting with a knife edge are right angles, and the impact resistance is low
Moreover, cutting with a knife edge produces microscopic chipping at the end of the chip, so the resulting chip has low flexural strength

Method used

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  • Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device
  • Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device
  • Method of manufacturing semiconductor chip, semiconductor chip, and semiconductor device

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Embodiment Construction

[0060] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0061] figure 1 It is a top view of a semiconductor substrate used in the method of one embodiment. figure 2 express figure 1 A partial cross-sectional view of a semiconductor device.

[0062] As shown in the figure, a plurality of element regions 12 are provided on a semiconductor substrate 10, and each element region 12 includes one or more semiconductor elements. These element regions 12 are arranged separately from each other. Each element region 12 is covered and protected by an etching mask 14 .

[0063] The semiconductor elements included in the element region 12 are, for example, transistors, diodes, light emitting diodes, or semiconductor lasers. The element region 12 may further include capacitors, wiring, and the like.

[0064]A region between adjacent element regions 12 is an exposed region 18 where the surface of the semiconductor substrate 10 is exp...

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Abstract

A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby dividing the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.

Description

[0001] This application is based on and enjoys the priority of Japanese Patent Application No. 2013-235470 filed on November 13, 2013, the entire contents of which are hereby incorporated by reference. technical field [0002] Embodiments of the present invention relate to a method of manufacturing a semiconductor chip, a semiconductor chip, and a semiconductor device. Background technique [0003] Singulation from a semiconductor substrate to chips generally uses blade dicing in which a rotating blade mechanically cuts a wafer. In blade dicing, a plurality of dicing grooves are sequentially formed on a semiconductor substrate, and the semiconductor substrate is singulated into chips. Therefore, there is a problem in blade dicing that if the chip size is reduced and the number of dicing grooves (the number of lines) is increased, the dicing time becomes longer in proportion to the number of lines. [0004] In addition, the corners of chips obtained by cutting with a knife e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/78H01L23/28
CPCH01L24/32H01L2224/32245H01L2224/48091H01L2224/48247H01L2224/73265H01L2224/83191H01L2924/10156H01L2924/00014H01L2924/00H01L2924/00012H01L21/304H01L21/30625H01L21/3065H01L21/76H01L21/78
Inventor 浅野佑策樋口和人富冈泰造井口知洋
Owner KK TOSHIBA
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