A Multi-Core Cryptographic Processor Based on Task Number Scheduling Control Mechanism

A scheduling control and processor technology, applied in the field of password analysis, can solve the problem of low transmission efficiency of the interface transmission layer, achieve the effect of improving flexibility and ensuring data transmission efficiency

Active Publication Date: 2017-10-24
THE PLA INFORMATION ENG UNIV
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Problems solved by technology

[0003] In view of this, the present application provides a multi-core cryptographic processor based on a task number scheduling control mechanism, which is used to solve the problem of low transmission efficiency of the multi-core cryptographic processor interface transmission layer in the prior art

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  • A Multi-Core Cryptographic Processor Based on Task Number Scheduling Control Mechanism
  • A Multi-Core Cryptographic Processor Based on Task Number Scheduling Control Mechanism
  • A Multi-Core Cryptographic Processor Based on Task Number Scheduling Control Mechanism

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Embodiment Construction

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0033] figure 1 It is a structural diagram of a multi-core cryptographic processor with a task number-based scheduling control mechanism disclosed in the embodiment of the present application.

[0034] see figure 1 , the embodiment of the present application discloses a multi-core cryptographic processor based on the task mapping mechanism of the central scheduler and the scheduling control mechanism based on the task number, including: an input cache 1 and a...

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Abstract

This application discloses a multi-core cryptographic processor based on a task number scheduling control mechanism, including: an input cache, an output cache, a central scheduler, and a cryptographic processor group. The central scheduler includes: an input microcontroller, an output microcontroller The controller and the hardware analysis unit, the hardware analysis unit is used to analyze the data packet header according to the data information in the preset boot list, and send the dispatching instructions obtained by the analysis to match the input order of the data packets to the input microcontroller, The analyzed identification information used to characterize the type of the data packet is sent to the output microcontroller; the identification information used to characterize the input sequence of the data packet and the corresponding scheduling instruction used to characterize the subtask allocation program are stored in the boot list . The above solution uses a limited-length packet header to call the subtask allocation program of the central scheduler through the task list, so as to complete the processing of the data packet, and realize the input of very little control information to drive the complex operation process.

Description

technical field [0001] The present application relates to the technical field of cipher analysis, and more specifically, relates to a multi-core cipher processor with a scheduling control mechanism based on task numbers. Background technique [0002] In the prior art, a multi-core cryptographic processor is usually used to process cryptographic information. For the internal control mechanism of a traditional multi-core cryptographic processor, its control information comes from the packet header of externally input data. However, the fixed-length (generally 32bits) dedicated cryptographic communication protocol has a limited number of headers, and the internal control process of the multi-core cryptographic operation module is complicated. Design a 32bits packet header for all the data, otherwise, the transmission efficiency of the interface transport layer will be seriously reduced, how to improve the transmission efficiency of the interface transport layer has become one o...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/46
Inventor 李伟李军伟戴乐育戴紫彬陈韬马超杜怡然
Owner THE PLA INFORMATION ENG UNIV
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