Unreliability test optimizing method based on grouping genetic algorithm

A genetic algorithm and group coding technology, applied in the field of board-level circuit fault diagnosis, which can solve problems such as large amount of calculation and many constraints.

Inactive Publication Date: 2015-06-10
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

However, in the case of sub-process testing, due to the large number of constraints, the amount of calculation required for testing and optimization using this method is very large

Method used

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  • Unreliability test optimizing method based on grouping genetic algorithm
  • Unreliability test optimizing method based on grouping genetic algorithm
  • Unreliability test optimizing method based on grouping genetic algorithm

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Embodiment

[0043] figure 2 It is a specific implementation flow chart of the unreliable testing optimization method based on block coding genetic algorithm of the present invention. Such as figure 2 Shown, the present invention is based on the unreliable test optimal method of block coding genetic algorithm and comprises the following steps:

[0044] S201: Set the serial number k of the testing process=1.

[0045] S202: Generate an initial population:

[0046] All tests under the kth test process are regarded as a group, and the coding of each individual chromosome in the population is the Boolean vector corresponding to the different test sets of all tests in the group, and X individuals are randomly generated according to the preset population size X.

[0047] In the process of testing a board-level circuit system, a total of |T| tests are used, and the entire test process is divided into K test procedures, which use |T 1 |a test, used in process 2 |T 2 |a test, and so on, the |T ...

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Abstract

The invention discloses an unreliability test optimizing method based on the grouping genetic algorithm. The method comprises taking all tests under every test procedure as a group; applying the genetic algorithm to every group to obtain the optimal test set under the corresponding test procedure, wherein in the genetic algorithm, the setting rules of an individual fitness function includes that, when a target detection rate selected to be tested in a test set corresponding to an individual chromosome code does not reach the target detection rate in a preset test procedure, the fitness value is zero, otherwise, the lower the test cost sum selected to be tested in the test value corresponding to the individual chromosome code is, the greater the value of the fitness function is; combining the optimal test set obtained under every test procedure to obtain a general test set, and if the detection rate of the general test set does not reach a general target detection rate, adding in unselected tests one by one until the detection rate of the general test rate meets the general target detection rate. The unreliability test optimizing method based on the grouping genetic algorithm improves the optimizing efficiency under the condition of ensuring the precision.

Description

technical field [0001] The invention belongs to the technical field of fault diagnosis of board-level circuits, and more specifically relates to an unreliable test optimization method based on group coding genetic algorithm. Background technique [0002] In the fault diagnosis process of the board-level circuit system, due to the influence of various factors such as electromagnetic interference and environmental changes, the test results are not necessarily completely accurate. If these uncertain factors are ignored in the actual testing process, it is likely to lead to wrong test results. Misdiagnosis will generate additional testing costs. As the complexity of the system increases, the additional testing costs are likely to exceed the cost of the test itself. It is particularly important to consider the unreliability of the test itself. During board-level circuit testing, the entire testing process often requires multiple testing procedures to complete, and each testing ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G06N3/12
Inventor 杨成林焦志敏刘震
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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