Memory chip scrambling code verification method

Abstract

The invention discloses a memory chip scrambling code verification method, which comprises the following steps: the first step is to select a packaged sample chip, and grind the sample chip from the back according to the thickness of the chip; the second step is to use chemical corrosion to continue Corrosion the back of the sample chip; the third step is to physically damage the storage area and record the physical address of the physical damage; the fourth step is to add a protective cover to the back of the sample chip and transfer it to a manual test machine for manual testing; the fifth step is to select Repeat the above steps for 2 to 20 sample chips, test different positions of the storage area for each sample chip, find out the failed electrical address, and calculate the corresponding relationship between the physical address and the electrical address based on the physical address in the third step.

Description

technical field [0001] The invention relates to the field of integrated circuit failure analysis, in particular to a memory chip scrambling code verification method. Background technique [0002] For memory chips, whether it is a volatile memory or a non-volatile memory, during the manufacturing and use stages, failure modes such as single bit, multiple bits, entire row of bits, and entire column of bits may be encountered, affecting mass production and terminals. customer use. To find the root cause of the failure, it is necessary to perform a physical failure analysis on the chip, that is, to find out the actual physical address of the failed bit on the chip, and conduct a targeted physical dissection to find the root cause of the failure. [0003] For the physical dissection of the memory chip, it is generally necessary to perform scrambling code verification first, that is, to find out the correspondence between the electrical address and the physical address. The trad...

AI Technical Summary

Problems solved by technology

However, with the increase of the chip wiring level and the customer's encryption protection measures for the chip (generally adding a metal layer encryption network on the front of the chip), there are many control circuit traces above the memory. Physical damage would render the entire memory area inoperable, let alone cracked

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