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A CMOS on-chip DC negative voltage generating circuit

A technology for generating circuits and negative voltages, applied to electrical components, conversion equipment without intermediate conversion to AC, code conversion, etc., can solve problems such as inability to provide DC negative voltage

Active Publication Date: 2017-08-25
NO 24 RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Aiming at the technical problems existing in the prior art, the present invention provides a CMOS on-chip DC negative voltage generation circuit, which can solve the problem that the existing CMOS analog / hybrid integrated circuit cannot provide DC negative voltage

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  • A CMOS on-chip DC negative voltage generating circuit
  • A CMOS on-chip DC negative voltage generating circuit
  • A CMOS on-chip DC negative voltage generating circuit

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Embodiment Construction

[0032] In order to make the technical means, creative features, goals and effects achieved by the present invention easy to understand, the present invention will be further described below in conjunction with specific illustrations.

[0033] Please refer to figure 2 As shown, the present invention provides a CMOS on-chip DC negative voltage generating circuit, including a charging unit 1, a clock unit 2, a charge pump unit 3, an output unit 4 and a charge storage unit 5; wherein,

[0034] The charging unit 1 is configured to charge the charge pump unit 3;

[0035] The clock unit 2 is configured to provide the required clock signal to the charge pump unit 3;

[0036] The charge pump unit 3 is used to generate a negative pulse voltage whose amplitude is equal to the positive power supply voltage;

[0037] The output unit 4 is configured to convert the negative pulse voltage generated by the charge pump unit 3 into a DC negative voltage, the magnitude of which is equal to the...

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PUM

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Abstract

A CMOS on-chip direct-current negative voltage generation circuit, comprising a charging unit (1), a clock unit (2), a charge pump unit (3), an output unit (4) and a charge storage unit (5). The charging unit (1) is used for charging the charge pump unit (3); the clock unit (2) is used for providing needed clock signals to the charge pump unit (3); the charge pump unit (3) is used for generating a negative impulse voltage that is equal to a positive supply voltage in amplitude; the output unit (4) is used for converting the negative impulse voltage generated by the charge pump unit (3) into a direct-current negative voltage, and the direct-current negative voltage is equal to the positive supply voltage; the charge storage unit (5) is used for storing charges brought by the charge pump unit (3) to a negative potential, and meanwhile the direct-current negative voltage output by the output unit (4) is kept stable in the working process of a CMOS chip. The problem that the direct-current negative voltage is generated inside a chip under the condition that the CMOS chip has single direct-current positive power supply is solved.

Description

technical field [0001] The invention belongs to the field of analog / mixed signal integrated circuits, and in particular relates to a CMOS on-chip DC negative voltage generation circuit. Background technique [0002] Today's integrated circuit manufacturing process - Complementary Metal Oxide Semiconductor (CMOS) process, the substrate is a P-type semiconductor. In order to achieve effective isolation between devices, the CMOS integrated circuit chip substrate is connected to the lowest potential - ground potential, and is powered by a positive power supply voltage. [0003] As the feature size of the CMOS process develops towards deep submicron (below 90nm), the chip power supply voltage is getting lower and lower, even lower than 1V. Under such a low power supply voltage, traditional analog circuit structures (such as operational amplifiers, current sources, etc.) will not work properly. Therefore, in order to make the traditional analog circuit structure work normally un...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02M3/07
CPCH03M1/54
Inventor 胡蓉彬王永禄胡刚毅陈光炳王育新付东兵张正平朱璨
Owner NO 24 RES INST OF CETC
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