Read method for responding to FLASH chip abnormal power-down

A chip and abnormal technology, applied in the field of memory, can solve the problems of reducing the reliability of FLASH chips, reducing the accuracy of data recorded by FLASH chips, and misreading of FLASH chips, so as to reduce misreading, improve reliability, and improve accuracy.

Active Publication Date: 2015-07-01
GIGADEVICE SEMICON (BEIJING) INC
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  • Abstract
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  • Claims
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Problems solved by technology

Because there is a memory cell with a large leakage current in the erasing area, when the memory cell on the bit line BL where the large leakage current memory cell is located is read or verified, misreading will occur, resulting in the reading of the FLASH chip. Misreading of data reduces the accuracy of data recorded by the FLASH chip, thereby reducing the reliability of the FLASH chip

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  • Read method for responding to FLASH chip abnormal power-down
  • Read method for responding to FLASH chip abnormal power-down
  • Read method for responding to FLASH chip abnormal power-down

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Embodiment Construction

[0025] The present invention will be described in more detail and complete below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only parts related to the present invention are shown in the drawings but not all content.

[0026] FLASH is composed of storage units (cells). Usually, a memory cell includes source (source, S), drain (drain, D), control gate (controlling gate, CG), and floating gate (floating gate, FG), and the control gate can be used for Connect to the reference voltage VG. If the drain is connected to the reference voltage VD, the voltage VG is applied to the control gate CG and the source S is connected to the ground, the memory cell realizes the channel hot electron injection programming operation. For eras...

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Abstract

The present invention relates to the memory technical field, and in particular relates to a read method for responding to FLASH chip abnormal power-down. The read method for responding to FLASH chip abnormal power-down is as follows: reading a FLASH chip power-down protection unit; wherein the power-down protection unit is used for recording address information of a current erase area in a FLASH chip storage array when a FLASH chip abnormally powers down during erase process; when the power-down protection unit stores address information, reading the address information; when the address information is same as the address information of a pre-read area, performing read correction on a storage array area corresponding to the address information, wherein the read correction is adjustment of read current during read; and after the read correction, reading the pre-read area. According to the read method for responding to FLASH chip abnormal power-down, after the read correction of a storage unit which is not erasure-corrected during abnormal power-down, the pre-read area is read, misreading during reading can be reduced, and the reliability of the FLASH chip can be improved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a reading method for dealing with abnormal power failure of a FLASH chip. Background technique [0002] FLASH (flash memory) chips include NAND-type FLASH chips and NOR-type FLASH chips. The use of FLASH chips refers to the process of repeated erasing, programming and reading of FLASH chips. [0003] figure 1 Shown is a schematic diagram of the structure of a NOR-type FLASH storage array in the prior art; refer to figure 1 , including power supply lines SL1-SLn, bit lines BL1-BLn, word lines WL1-WLn (where n is an integer greater than 1) and memory cells 11 . Taking the erasing of the erasing area 12 as an example, the erasing area 12 is within the area defined by the bit lines BL1-BLn and the word lines WL2-WL4. In order to erase the erasing area 12, a stress negative voltage V is applied to the word lines WL2-WL4 Erase , the power lines SL2-SL4 and the bit lines BL1-BLn are ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/10G11C16/14
Inventor 胡洪洪杰王林凯
Owner GIGADEVICE SEMICON (BEIJING) INC
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