Modular packaged integrated circuit chip and manufacturing method thereof

Abstract

The present invention provides a modular packaged integrated circuit chip and a manufacturing method thereof. The method includes: S1, manufacturing several first bare chips and several second bare chips according to the function and performance requirements of the target chip, the first bare chips The shape of the chip and the second die is a square or a rectangle composed of an integer number of preset reference rectangles, and the second die is smaller than the first die, and several interfaces are provided on the first die, so There is a preset distance between the interfaces, the interfaces form an interface matrix, the number of the interfaces is greater than the number of the manufactured second die, and the preset distance is greater than the maximum size of the second die ; S2, select a first die and at least one second die from the plurality of first dies and several second dies produced in step S1; S3, select the first die selected in step S2 performing modular packaging with the second die to obtain the target chip.

Description

technical field [0001] The invention relates to the field of system-in-package manufacturing, in particular to a modular packaged integrated circuit chip and a manufacturing method thereof. Background technique [0002] With the continuous development of the chip manufacturing process, the continuous improvement of the integration level, and the increasingly complex functions of the chip, the difficulty of chip design is also increasing day by day. The SiP (System in Package, system-in-package) technology that combines mature bare chips into a chip is an emerging technology that emerged as the times require. This technology refers to the integration of bare chips with multiple functions (including central processing unit, coprocessor, memory, resistors, capacitors, inductors, etc.) into one package according to needs, and finally realizes complete functions. It should be pointed out that SiP is similar to SoC (System on a Chip), but SiP uses different chips to be packaged s...

AI Technical Summary

Problems solved by technology

[0004] System-in-package technology has many advantages, especially in quickly completing the research and development of chip products. The original die cannot be replaced directly when updating and upgrading

At present, when the chip needs to be upgraded, only the whole chip can be replaced, which results in more chip design time and prolongs the time required for product upgrades

Moreover, the replaced chip also caused a waste of resources, and did not realize the effective utilization of the bare chip.

The impact of the above time delays and waste of resources will be significant when upgrading chips for high-volume products

[0005] To sum up, the current common chip system-in-package methods generally have the problems of narrow application range, low plasticity, and high upgrade cost.

Images