Method for planning interlocking micro-bump matrix of overlapped type three-dimensional integrated chips
An integrated chip and three-dimensional integration technology, which is applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems that are difficult to meet Moore's Law, and achieve the effects of strong intuition, short running time, and high accuracy
Inactive Publication Date: 2015-07-29
TSINGHUA UNIV
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Abstract
The invention relates to a method for planning an interlocking micro-bump matrix of overlapped type three-dimensional integrated chips, and belongs to the technical field of computer aided design of optimum design of three-dimensional wiring of integrated circuit chips. The method mainly comprises the following steps of when the corresponding positions and numbers of fins and micro-bumps of an upper layer and a lower layer are given, establishing an enclosing frame for each group of fins; establishing a matrix A and a matrix B for representing the position relationship of the micro-bumps and the enclosing frame, wherein elements in the matrix A are used for representing whether the micro-bumps exist in the enclosing frame or not, and elements in the matrix B are used for representing the sum of Manhattan distances between the micro-bumps and the enclosing frame; utilizing a Hungary algorithm to realize unique corresponding between the micro-bumps and the surrounding frame and enable the sum of the Manhattan distances to be minimum; according to the results of the Hungary algorithm, pre-connecting the micro-bumps and the fins; comprehensively utilizing an interchange and winding method, and eliminating the crossing of the distributed micro-bumps. The method has the advantages that the running time is short, the accuracy is high, and the intuition is strong.
Application Domain
Special data processing applications
Technology Topic
Optimal designIntegrated circuit +4
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