Method for planning interlocking micro-bump matrix of overlapped type three-dimensional integrated chips

Abstract

The invention relates to a method for planning an interlocking micro-bump matrix of overlapped type three-dimensional integrated chips, and belongs to the technical field of computer aided design of optimum design of three-dimensional wiring of integrated circuit chips. The method mainly comprises the following steps of when the corresponding positions and numbers of fins and micro-bumps of an upper layer and a lower layer are given, establishing an enclosing frame for each group of fins; establishing a matrix A and a matrix B for representing the position relationship of the micro-bumps and the enclosing frame, wherein elements in the matrix A are used for representing whether the micro-bumps exist in the enclosing frame or not, and elements in the matrix B are used for representing the sum of Manhattan distances between the micro-bumps and the enclosing frame; utilizing a Hungary algorithm to realize unique corresponding between the micro-bumps and the surrounding frame and enable the sum of the Manhattan distances to be minimum; according to the results of the Hungary algorithm, pre-connecting the micro-bumps and the fins; comprehensively utilizing an interchange and winding method, and eliminating the crossing of the distributed micro-bumps. The method has the advantages that the running time is short, the accuracy is high, and the intuition is strong.

Description

technical field [0001] The planning method of interconnected micro-bump matrix between stacked three-dimensional integrated chips belongs to the field of computer-aided design of integrated circuits, especially relates to the field of three-dimensional wiring. Background technique [0002] With the development of VLSI design technology and technology, the size and scale of devices in integrated circuits are getting smaller and smaller, and the scale and integration of chips are getting bigger and bigger. With the improvement of component integration scale, in the current VLSI circuit, the delay of signal propagation and power consumption are becoming more and more serious, and it is difficult to meet the requirements of Moore's Law. In order to solve these problems, three-dimensional chip technology came into being. [0003] Three-dimensional chip technology is a new technology. This technology integrates multiple chips vertically in three-dimensional space, which can impro...

AI Technical Summary

Problems solved by technology

With the improvement of component integration scale, in the current VLSI circuit, the problem of signal propagation delay and power consumption is becoming more and more serious, and it is difficult to meet the requirements of Moore's Law.

Images