Method for planning interlocking micro-bump matrix of overlapped type three-dimensional integrated chips
An integrated chip and three-dimensional integration technology, which is applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems that are difficult to meet Moore's Law, and achieve the effects of strong intuition, short running time, and high accuracy
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[0042] In three-dimensional design, micro bump technology plays an auxiliary role in the connection of the upper and lower pins. The present invention can connect the micro bumps and pins in the middle layer according to different initial chip states. The connection between the micro bumps and the pins must be in the horizontal or vertical direction, and make the connection the shortest and not Cross each other.
[0043] In order to make the problem concise, we transformed the three-dimensional problem into a two-dimensional problem for solution.
[0044] The method for planning the interconnected micro-bump matrix between stacked three-dimensional integrated chips is characterized in that it is implemented in a computer according to the following steps in sequence:
[0045] Step (1), initialization, given a n, n represents the number of pin pairs, the total number of pins is 2n. Use random number simulation to generate the coordinates of these 2n points. Each coordinate is an int...
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