Gate driving circuit, display panel and touch display device

A gate drive circuit and gate drive technology, applied in the fields of gate drive circuits, display panels and touch display devices, can solve problems such as abnormal output of GOA circuits and serious attenuation of input signals

Active Publication Date: 2015-08-05
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, when the display needs to divide the display time of one frame into multiple time periods, and there needs to be a certain time interval between each time period, the above-mentioned GOA circuit wi

Method used

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  • Gate driving circuit, display panel and touch display device
  • Gate driving circuit, display panel and touch display device
  • Gate driving circuit, display panel and touch display device

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Embodiment Construction

[0040] The specific implementations of the gate driving circuit, the display panel, and the touch display device provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] A gate driving circuit provided by an embodiment of the present invention, such as figure 2 As shown, it includes at least two stages of gate drive sub-circuit 1 ( figure 2 Take the two-stage gate drive sub-circuit as an example); among them, each stage of the gate drive sub-circuit 1 includes multiple cascaded shift registers: SR(1), SR(2)...SR(n) …SR(N-1), SR(N) (a total of N shift registers, 1≤n≤N), each level of gate drive sub-circuit 1 is used when the first level of shift register SR(1) receives After the input signal input by the corresponding input signal terminal Input, the signal output terminal Output of each level of shift register sequentially outputs the gate drive signal;

[0042] Except for the last-stage gate driv...

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PUM

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Abstract

The invention discloses a gate driving circuit, a display panel and a touch display device. A voltage maintaining unit is arranged between two adjacent levels of gate driving sub circuits in the gate driving circuit to ensure that the potential at an input signal control end of a first-level shift register in a next-level gate driving sub circuit is the potential of a gate driving signal after a last-level shift register in a previous-level gate driving sub circuit connected with the voltage maintaining unit outputs a gate driving signal and before a first-level shift register in a next-level gate driving sub circuit connected with the voltage maintaining unit outputs a gate driving signal. Thus, no matter how long the interval between the time when a gate driving sub circuit outputs a gate driving signal and the time when an adjacent gate driving circuit outputs a gate driving circuit, the potential at an input signal control end of a first-level shift register in a next-level gate driving sub circuit can be maintained as the potential of a gate driving signal instead of attenuating with time, so that normal output of gate driving sub circuits at all levels is ensured.

Description

Technical field [0001] The invention relates to the field of display technology, in particular to a gate drive circuit, a display panel and a touch display device. Background technique [0002] In a thin film transistor display, a gate driving signal is usually provided to the gate of each thin film transistor (TFT, Thin Film Transistor) in the pixel area through a gate driving circuit. The gate drive circuit can be formed on the array substrate of the liquid crystal display through an array process, that is, an array substrate line drive (Gate Driver on Array, GOA) process. This integrated process not only saves costs, but also enables a liquid crystal panel (Panel) The symmetrical and beautiful design on both sides also eliminates the bonding area of ​​the gate integrated circuit (IC) and the fan-out wiring space, so that a narrow frame design can be realized. [0003] Existing GOA circuits such as figure 1 As shown, it is composed of multiple shift registers: SR(1), SR(2), ...S...

Claims

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Application Information

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IPC IPC(8): G09G3/36G06F3/041
CPCG06F3/04184G09G3/3677G09G2310/0286G09G2310/08G06F3/0412G06F3/04166G09G2320/0223G11C19/00
Inventor 陈希
Owner BOE TECH GRP CO LTD
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