A Data Access System Based on 8051 Single Chip Computer with External Ram Interface

Abstract

The invention particularly relates to an 8051 singlechip-based plug-in RAM (random access memory) interface data access system. The 8051 singlechip-based plug-in RAM interface data access system comprises an 8051 singlechip, a Wishbone master module, an FIFO (First In First Out) module, a register module, a RAM module, an interrupt control module and external devices; the Wishbone master module is connected to the 8051 singlechip, the FIFO module, the register module and the RAM module, and the FIFO module and the register module are connected to the 8051 singlechip through the interrupt control module. By means of a plug-in RAM interface, the 8051 singlechip-based plug-in RAM interface data access system can correctly read and write the different submodules, i.e. the register module, the FIFO module, the RAM module and the like, and can be compatible with the submodules with different read delays; in addition, the 8051 singlechip-based plug-in RAM interface data access system is also added with scratch-pad registers, and adopts the method of two read commands and interrupt delay, so that the 8051 singlechip can correctly read the data of each submodule. The 8051 singlechip-based plug-in RAM interface data access system has the characteristics of high read delay compatibility, easiness in implementation and the like, and has a broad application prospect.

Description

technical field [0001] The invention relates to the technical field of single-chip microcomputer application, in particular to an external RAM interface data access system based on an 8051 single-chip microcomputer. Background technique [0002] The Wishbone bus completes interconnection by establishing a common interface between IP cores, and can be used to interconnect soft cores, solid cores, and hard cores. Compared with other IP core interface specifications, the Wishbone interface specification is simple, open, efficient, easy to implement, and completely free. Based on the above advantages, the Wishbone bus is used for interface design. However, when the Wishbone bus is used as the system bus protocol of the 8051 single-chip microcomputer, the number of GPIOs of the 8051 single-chip microcomputer is not enough. [0003] The 8051 single-chip microcomputer reads the data of the sub-module, and requires the data to be read back at the rising edge of the current clock o...

AI Technical Summary

Problems solved by technology

External devices will cause data changes in FIFO modules and register modules, resulting in interrupts. The 8051 MCU executes the interrupt program to read new data from the sub-modules, but interrupts can occur at any time, and may interrupt the 8051 MCU. The read operation command of the interrupted program cannot be executed correctly after the execution of the interrupt program is completed.

[0004] Aiming at the insufficient number of 8051 single-chip GPIOs and the failure of the single-chip to correctly execute read operation commands caused by interruptions, the present invention proposes an external RAM interface data access system based on the 8051 single-chip

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