Memory management method and equipment

Abstract

Provided are a memory management method and device. The method comprises: receiving, by a memory manager, a memory access request, the memory access request carrying a virtual address; if the memory manager does not find a page table entry corresponding to the virtual address in a translation lookaside buffer (TLB) and a memory, judging the missing page type of the virtual address; if the missing page type of the virtual address is a missing blank page, allocating, by the memory manager, a corresponding page to the virtual address, the missing blank page referring to the case where a corresponding page is not allocated to the virtual address; and updating, by the memory manager, the page table entry corresponding to the virtual address into the memory and the TLB. By judging the missing page type of the virtual address, when a blank page is missed, the memory manager does not generate missing page interrupt, but allocates the corresponding page to the virtual address, so that the memory management efficiency is improved by reducing the number of times of occurrence of missing page interrupt.

Description

Technical field [0001] The embodiments of the present invention relate to computer technology, and in particular to a method and device for memory management. Background technique [0002] In modern computer systems, memory management tasks are jointly implemented by an operating system, a memory management unit (Memory Management Unit, MMU), and a page table cache (TranslationLookasideBuffer, TLB). [0003] In the existing memory management process, the operating system is responsible for most of the memory management tasks, and the most frequently operated virtual and real address mapping and page checking tasks are implemented by hardware such as TLB and MMU. This memory management method has two inherent bottlenecks: (1) TLB and MMU are on the critical path of the processor accessing the cache. Each time the processor accesses the cache, it must first access the TLB. Once the TLB miss increases, the MMU will frequently check the page. , It is easy to cause system bottlenecks. ...

AI Technical Summary

Problems solved by technology

[0005] However, the processing method of the page fault interrupt is still bound to the processor. Whether the page is checked by the MMU hardware or the operating system, as long as the page check fails, a page fault interrupt will be generated, and the processor will waste a lot of time on processing the page fault. Interrupts, making memory management inefficient

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