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Embedded flash memory structure and preparation method thereof

An embedded and flash memory technology, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve problems such as difficult coupling ratio and reduction

Inactive Publication Date: 2015-12-09
WUHAN XINXIN SEMICON MFG CO LTD
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Problems solved by technology

[0003] This problem is solved by depositing a second tunnel oxide layer between the floating gate and the erasing gate to isolate the floating gate and the erasing gate. This method does improve the performance of embedded flash memory to a certain extent. Erase efficiency, however, it is difficult to continue to reduce the coupling ratio of the erasing gate to the floating gate by relying on this method

Method used

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  • Embedded flash memory structure and preparation method thereof
  • Embedded flash memory structure and preparation method thereof
  • Embedded flash memory structure and preparation method thereof

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Embodiment Construction

[0043] In order to facilitate the implementation of the present invention by those having ordinary knowledge in the field to which the present invention pertains, examples of the present invention will be described in detail with reference to the accompanying drawings shown below. However, the present invention can be implemented in various forms and is not limited to the examples described here. In order to more clearly describe the present invention, parts irrelevant to the description in the drawings are omitted; and, throughout the specification, similar drawing symbols are assigned to similar parts.

[0044] Throughout the description of the present invention, the "connection" of one part to another part includes not only "direct connection" but also "electrical connection" through other components.

[0045] In the entire description of the present invention, a certain part is located "above" another part, including not only the state where a certain part is connected to ...

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Abstract

The invention relates to the technical field of semiconductor devices, in particular to an embedded flash memory structure and a preparation method thereof. According to the preparation method, reduction of the coupling ratio of an erasing gate to a floating gate is achieved by optimizing the order of a technology and improving the technology before a second tunneling oxidation layer between the erasing gate and the floating gate deposits, so that the erasing efficiency of a 55nm embedded flash memory is effectively improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to an embedded flash memory structure and a preparation method thereof. Background technique [0002] As we all know, the coupling ratio between the erasing gate and the floating gate of 55nm embedded flash memory directly affects the erasing efficiency of embedded flash memory (eflash). In the current technology, silicon dioxide and nitrogen are deposited after the control gate is fabricated. Si sidewalls are formed, and then sidewalls are etched to form sidewall layers. Then, the spacer layer is used as self-alignment to etch the floating gate to form an overlapping area between the erasing gate and the floating gate. [0003] This problem is solved by depositing a second tunnel oxide layer between the floating gate and the erasing gate to isolate the floating gate and the erasing gate. This method does improve the performance of embedded flash memory to a certain e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H01L27/115H10B69/00
CPCH10B41/00H10B41/42
Inventor 罗清威周俊
Owner WUHAN XINXIN SEMICON MFG CO LTD
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