Embedded flash memory structure and manufacturing method thereof

Abstract

The invention discloses an embedded flash memory structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, forming a floating gate structure on the substrate; etching the floating gate structure, and forming a floating gate structure on the floating gate structure A groove is formed in the middle; a barrier layer is deposited, and the barrier layer covers the sidewall and the bottom of the groove; a first dielectric layer is formed on the barrier layer at the bottom of the groove; the barrier layer is removed, and the The blocking layer under the first dielectric layer; forming an erasing gate structure on the remaining blocking layer. The embedded flash memory structure formed in this way can reduce the coupling ratio between the erasing gate and the floating gate, and improve the erasing efficiency of the embedded flash memory structure; moreover, it can also improve the "smile effect" in the device, improve device performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an embedded flash memory structure and a manufacturing method thereof. Background technique [0002] Flash memory has become a research hotspot in non-volatile memory due to its convenience, high storage density, and good reliability. Since the first flash memory product came out in the 1980s, with the development of technology and the storage needs of various electronic products, flash memory has been widely used in mobile and communication devices such as mobile phones, notebooks, handheld computers and U disks. Today, flash memory has occupied most of the market share of non-volatile semiconductor memory, becoming the fastest growing non-volatile semiconductor memory. [0003] It is well known that the coupling ratio between the erase gate (EG) and the floating gate (FG) of the embedded flash memory structure directly affects the erasing efficiency of the ...

AI Technical Summary

Problems solved by technology

In the prior art, a layer of denser silicon dioxide is deposited between the floating gate and the erase gate. , this method improves the erasing efficiency of the embedded flash memory structure to a certain extent, but the coupling ratio between the erasing gate and the floating gate fabricated in this way is difficult to continue to decrease

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