A kind of embedded flash memory structure and preparation method thereof

Abstract

The present invention relates to the technical field of semiconductor devices, in particular to an embedded flash memory structure and a preparation method thereof. Firstly, a silicon substrate prepared with a first protruding structure and a second protruding structure is provided, and the protruding structure on the silicon substrate is Structurally, the first through hole and the second through hole are respectively etched, an oxide layer is prepared on the side wall of the first through hole, a gate oxide layer is prepared on the side wall of the second through hole, and then a wiper is prepared in the first through hole. Remove the gate, and prepare the word line gate in the second through hole. This method effectively improves the process before the deposition of the tunnel oxide layer between the erase gate and the floating gate, so as to achieve the coupling ratio of the erase gate to the floating gate. Reduced, thereby effectively improving the erasing efficiency of the 55nm embedded flash memory.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to an embedded flash memory structure and a preparation method thereof. Background technique [0002] As we all know, the coupling ratio between the erasing gate and the floating gate of 55nm embedded flash memory directly affects the erasing efficiency of embedded flash memory (eflash). In the current technology, silicon dioxide and nitrogen are deposited after the control gate is fabricated. Si sidewalls are formed, and then sidewalls are etched to form sidewall layers. Then, the spacer layer is used as self-alignment to etch the floating gate to form an overlapping area between the erasing gate and the floating gate. [0003] This problem is solved by depositing a tunnel oxide layer between the floating gate and the erasing gate to isolate the floating gate and the erasing gate. This method does improve the erasing of the embedded flash memory to a certain extent. ...

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Problems solved by technology

[0003] This problem is solved by depositing a tunnel oxide layer between the floating gate and the erasing gate to isolate the floating gate and the erasing gate. This method does improve the erasing of the embedded flash memory to a certain extent. efficiency, however, it is difficult to continue to reduce the coupling ratio of the erasing gate to the floating gate by relying on this method

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