Embedded flash memory structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, in particular to an embedded flash memory structure and a preparation method thereof. The method comprises the following steps: firstly, providing a silicon substrate with a first bump structure and a second bump structure; respectively etching the bump structures of the silicon substrate to form a first through hole and a second through hole; preparing an oxidation layer on the side wall of the first through hole, and preparing a gate oxidation layer on the side wall of the second through hole; and preparing an erasing gate in the first through hole, and preparing a word line gate in the second through hole. According to the method, the technology before a tunneling oxidation layer between the erasing gate and a floating gate deposits is effectively improved; and the coupling ratio between the erasing gate and the floating gate is reduced. Therefore, the erasing efficiency of a 55nm embedded flash memory is effectively improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to an embedded flash memory structure and a preparation method thereof. Background technique [0002] As we all know, the coupling ratio between the erasing gate and the floating gate of 55nm embedded flash memory directly affects the erasing efficiency of embedded flash memory (eflash). In the current technology, silicon dioxide and nitrogen are deposited after the control gate is fabricated. Si sidewalls are formed, and then sidewalls are etched to form sidewall layers. Then, the spacer layer is used as self-alignment to etch the floating gate to form an overlapping area between the erasing gate and the floating gate. [0003] This problem is solved by depositing a tunnel oxide layer between the floating gate and the erasing gate to isolate the floating gate and the erasing gate. This method does improve the erasing of the embedded flash memory to a certain extent. ...

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Problems solved by technology

[0003] This problem is solved by depositing a tunnel oxide layer between the floating gate and the erasing gate to isolate the floating gate and the erasing gate. This method does improve the erasing of the embedded flash memory to a certain extent. efficiency, however, it is difficult to continue to reduce the coupling ratio of the erasing gate to the floating gate by relying on this method

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