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Differential Sampling Circuit with Harmonic Cancellation

A sampling circuit and differential technology, applied in the field of differential sampling circuits

Active Publication Date: 2019-05-07
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, the sample-and-hold circuit at the input of the ADC may cause the generation of harmonic components due to the inherent nonlinearity of the MOS sampling switches, junction diodes, and sampling glitches

Method used

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  • Differential Sampling Circuit with Harmonic Cancellation
  • Differential Sampling Circuit with Harmonic Cancellation
  • Differential Sampling Circuit with Harmonic Cancellation

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0010] The described examples include compensation circuits for reducing or eliminating second harmonic content caused by phase imbalances in differential sampling circuits due to differential switching. Input imbalance in a differential circuit is caused by several factors such as board mismatch, driver transformer mismatch, etc. The compensation circuit provides a field effect transistor operating in saturation mode coupled in parallel with a differential switch of the sampling circuit operating in linear mode. By placing a saturation region transistor across the differential switch, the harmonic content flows not through the sampling capacitor of the sampling circuit but through the compensation circuit.

[0011] Fig. 1 shows a typical embodiment of a known sampling circuit 10 for differential inputs INP and INM (as used, eg in the front end of an analog-to-digital converter (ADC)). Figure 1 is a simplified representation and is intended to be illustrative only. Additiona...

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Abstract

The differential sampling circuit (100) includes a compensation circuit (140) for canceling harmonic content caused by phase imbalance. The compensation circuit (140) includes a pair of field effect transistors (142, 143) operating in saturation mode, each field effect transistor (142, 143) being coupled in parallel with the differential switch (122) of the sampling circuit (100), which is Works in linear mode. Saturation region transistors (142, 143) across the differential switch (122) allow harmonic content to flow through the compensation circuit (140) instead of the sampling capacitors (12, 13) of the sampling circuit (100).

Description

technical field [0001] The present invention relates generally to electronic circuits, and more particularly to differential sampling circuits with harmonic cancellation. Background technique [0002] An analog-to-digital converter (ADC) is used to generate a sequence of digital codes representing the strength of an input signal at corresponding points in time. ADCs can be implemented in various well-known forms, such as successive approximation (SAR) ADCs, pipelined ADCs, and the like. [0003] The term "spurious-free dynamic range" (SFDR) of an ADC generally quantifies the extent to which harmonic content is present in the output of the ADC. Ideally, harmonic content should be absent from the ADC output. According to a convention, SFDR is referred to as the ratio of the RMS (root mean square) amplitude of the carrier frequency (largest signal component or fundamental frequency) to the next largest noise or harmonic distortion component (components with frequencies that a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M3/00G05F3/02
CPCG11C27/02H03M1/1245
Inventor R·弗兰西斯
Owner TEXAS INSTR INC