A nsga-ii-based power and area optimization method for incompletely determined reed-muller circuits

Abstract

A method based on NSGA-II for power consumption and area optimization of incompletely determined Reed-Muller circuits, 1 converts incompletely determined Boolean logic functions into zero-polarity incompletely determined RM expressions; 2 converts incompletely determined Boolean logic functions 3. Establish the power consumption area estimation model; 4. Establish the power consumption area objective function; 5. Establish the fitness function related to the power consumption area; 6. Determine the constraint conditions; 7. Initialize the parameters; 8. Generate the initial population Execute non-dominated sorting; 9. Execute selective crossover and mutation to generate offspring populations; 10. Merge the parent and offspring populations to perform non-dominated sorting; 11 Calculate the degree of individual crowding in the non-dominated layer and form a new parent population; 12 pairs of new The parent population executes selective crossover and mutation to generate a new offspring population; 13 If the current evolutionary algebra is less than or equal to the maximum evolutionary algebra, return 10; otherwise, output the optimal solution set; 14 Select the best irrelevant item from the optimal solution set , to get the corresponding fully deterministic RM expression.

Description

technical field [0001] The invention relates to an optimization method for power consumption and area of ​​an incompletely determined Reed-Muller circuit, in particular to a method for optimizing power consumption and area of ​​an incompletely determined Reed-Muller circuit based on NSGA-II. The invention belongs to the technical field of logic functions and logic circuits. Background technique [0002] The logic function can be realized not only by Boolean logic based on AND / OR / NOT operation, but also by Reed-Muller (RM) logic based on AND / XOR or XNOR / OR operation. For some circuits, such as arithmetic circuits, parity check circuits, and communication circuits, where XOR operations are more frequent, compared with Boolean logic implementations, RM logic implementations have greater advantages in terms of power consumption, area, and speed. And because the change of a certain input of the XOR gate will directly cause the change of its output, the RM logic circuit also has ...

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Problems solved by technology

[0009] (2) The research on the optimization of RM logic circuits considering irrelevant items mainly focuses on the polarity conversion of RM expressions including irrelevant items and the simplification of logic function expressions. Few studies use irrelevant items to compare the power consumption of RM logic circuits Simultaneous optimization of area

However, because the traditional weighted summation method has various defects such as being unable to solve the non-convex Pareto front, the distribution of the solution is not uniform enough, it is necessary to manually set multiple sets of different weights and perform multiple operations to obtain the Pareto optimal solution set, etc. The RM logic circuit power consumption and area optimization method of the summation method is not effective, and has certain limitations in practical applications

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