Metastable state eliminating circuit used for TDC

Abstract

The invention belongs to the technical field of electronic circuits, and specifically relates to a metastable state eliminating circuit used for a TDC. The main structure of the metastable state eliminating circuit is composed of a first rising edge D trigger, a second rising edge D trigger, a third rising edge D trigger, a first falling edge D trigger and a second falling edge D trigger, wherein a D input end of the first rising edge D trigger and a D input end of the first falling edge D trigger are connected with external input signals; a Q output end of the second rising edge D trigger is connected with a clock signal input end of the third rising edge D trigger; and a Q output end of the second falling edge D trigger is connected with a D input end of the third rising edge D trigger. The metastable state eliminating circuit has the beneficial effects of being capable of effectively eliminating timing error caused by metastable state while ensuring that the result after time digital quantification and the traditional TDC have the same measuring range and resolution, and greatly improves reliability of TDC precision.

Description

technical field [0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a metastable state elimination circuit for TDC. Background technique [0002] Time interval measurement technology has a large number of applications in many fields. It is not only widely used in atomic physics, laser ranging, positioning and timing, but also in the field of time interval measurement technology and automatic detection equipment; in addition, in the defense industry, time interval measurement is an important means of identification and detection , the requirements for accuracy are very strict, even reaching the level of picoseconds. Therefore, a high-precision TDC circuit plays an important role. [0003] A typical all-digital time converter uses a DLL and a counter two-stage structure to quantify time. The basic idea is to measure the time between the rising edge of the start signal and the rising edge of the stop signal by counting a c...

AI Technical Summary

Problems solved by technology

[0005] Due to the setup and hold time of the D flip-flop during sampling, start samples d[7:0] at the position ①②. Since d[7] is in a flipped state, a metastable state may occur, resulting in an error in the sampling result.

Thus ΔT start possible from T clk to 0ns transition; or conversely, it is possible to go from 0ns to T clk The jump of the TDC causes a large deviation in the counting of the TDC

Images