Successive approximation ADC ultra-low power consumption capacitor array and logic control method thereof

Abstract

The invention discloses a successive approximation ADC ultra-low power consumption capacitor array and a logic control method thereof and belongs to the successive approximation ADC ultra-low power consumption design technical field. The successive approximation ADC ultra-low power consumption capacitor array includes a binary capacitor array, a switch array and references (Vref, Vcm=Vref / 2 and Gnd=0); the logic control method is a novel logic control method. According to the method, capacitor upper polar plate sampling, switch control time sequence initialization, parasitic capacitance power consumption reduction and capacitor monotonic switching are used in combination. The average energy consumption of the capacitor array is only 1.2% of a traditional charge redistribution structure. The capacitor array has advantages of simple structure, low power consumption, small size and so on. When the capacitor array and the logic control method thereof of the invention are applied to successive approximation ADC, power consumption can be significantly reduced. Under the same conversion accuracy, the size of the capacitor array of the invention can be decreased, so that improvement of A / D conversion rate can be benefitted.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an ultra-low power consumption capacitor array for successive approximation ADC and a logic control method thereof. Background technique [0002] The charge redistribution type successive approximation (SAR) ADC with capacitor array as the main structure has been widely used due to its low power consumption. Especially in implantable bioelectronic systems for neural signal recording (EEG, ECOG, etc.), the ADC embedded in it needs to have ultra-low power consumption and miniaturization. The scale of the traditional charge redistribution SARADC capacitor array varies with The number of ADC bits increases exponentially, which is not conducive to area, power consumption and speed optimization. figure 1 Shown is the traditional N-bit fully differential charge redistribution SARADC structure, and its capacitor array includes a total of 2 N+1 unit capacitance. ...

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Problems solved by technology

On the one hand, due to the constraints of matching accuracy and noise performance, not only the circuit area is large, the process cost is high, but also the dynamic power consumption of the capacitor array is relatively large; on the other hand, the large-scale capacitor array leads to a large input capacitance of SARADC. It not only affects the improvement of ADC sampling rate, but also requires the analog front-end (AFE) circuit to have a strong driving capability, which affects the low power consumption optimization of the AFE circuit and the entire SoC

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