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Method for forming double mosaic structures

A dual damascene structure and graphics technology, which is applied in the fields of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems of poor performance of the dual damascene structure

Active Publication Date: 2016-01-06
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] The problem solved by the present invention is that the performance of the double damascene structure formed by the method of the prior art is not good

Method used

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  • Method for forming double mosaic structures
  • Method for forming double mosaic structures
  • Method for forming double mosaic structures

Examples

Experimental program
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Effect test

Embodiment Construction

[0042] After research and discovery, the reasons for the poor performance of the dual damascene structure formed by the method of the prior art are as follows:

[0043] refer to image 3 The width H1 of the second opening 106 in the titanium nitride layer 103 is equal to the sum of the width W1 of the two third openings 111 and the width W2 of the photoresist between the two adjacent third openings 111 . refer to Figure 5 After forming two first through holes 112 in the low-k dielectric layer 102, the second opening 106 is exposed at the sidewall of one of the first through holes 112 (refer to figure 2 ) of one side wall; the other side wall of the first through hole 112 also exposes the other side wall of the second opening 106 . That is, from Figure 5As shown in the sectional view, one side wall boundary of the second opening 106 is on the same straight line as the side wall boundary of a first through hole 112, and the other side wall boundary of the second opening 10...

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Abstract

The invention discloses a method for forming double mosaic structures, and the method comprises the steps: providing a substrate; forming a first dielectric layer on the substrate; forming a first through hole in the first dielectric layer, wherein the bottom of the first through hole is exposed out of the substrate; filling the first through hole with a second dielectric layer, wherein the second dielectric layer covers the first dielectric layer, and the etching selection ratio of the second dielectric layer to the first dielectric layer is greater than or equal to 10: 1; forming a trench in the second dielectric layer, wherein the bottom of the trench enables the second dielectric layer in the first through hole to be exposed; forming a second through hole in the second dielectric layer in the first through hole after the trench is formed, wherein the second through hole is communicated with the trench, and is exposed out of the substrate; and filling the trench and the second through hole with a conductive layer. The double mosaic structures formed through the method can improve the performance of a semiconductor device formed subsequently.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a double damascene structure. Background technique [0002] With the rapid development of semiconductor device manufacturing technology, semiconductor devices already have deep submicron structures. As the number of devices contained in integrated circuits continues to increase, and the size of devices continues to shrink due to the increase in integration, the high-performance, high-density connections between devices are not only performed in a single interconnection layer, but also in multiple layers. interconnection between. Therefore, a multilayer interconnection structure is generally provided for connecting semiconductor devices, wherein a plurality of interconnection layers are stacked on each other, and an interlayer dielectric layer is interposed therebetween for insulation. In particular, a multi-layer interconnection structure formed by a dual-dama...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768
Inventor 张城龙张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP
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