Systems and methods for adjusting clock frequency

Abstract

One aspect of the disclosure discloses adjusting a clock frequency. One aspect of the present disclosure provides a computer system. In one embodiment, a computer system includes a clock generator, at least one processor, and a clock frequency controller. The clock generator is configured to provide a clock signal having a clock frequency. At least one processor is configured to receive the clock signal and operate at the speed of the clock frequency. The clock frequency controller is configured to receive efficiency information indicative of a current efficiency of at least one processor. The clock frequency controller is further configured to receive a request from the processor to process a target number of processor instructions within a specified time period. The clock frequency controller is further configured to output a frequency control signal to the clock generator for controlling the clock frequency accordingly.

Description

technical field [0001] This application relates to computer systems with adjustable clock frequency. Background technique [0002] Many computer systems have multiple processors arranged to execute instructions. Each processor is arranged to receive a clock signal and to set its operating frequency according to it. In other words, the frequency of the processing cycle of the processor is set according to the frequency of the clock signal. Typically, the operating frequency of the processor is equal to the frequency of the clock signal. The operating frequency determines how quickly the processor processes instructions. The higher the frequency of the clock signal input to the processor, the faster the instructions will be executed by the processor in real time. [0003] Processing cycles can be spent on useful work such as, for example, instruction execution, intentional idle, and useless work, such as for example when hazards are introduced into the pipeline or when wai...

AI Technical Summary

Problems solved by technology

One example of a risk is that the instruction pipeline needs to be flushed due to a branch misprediction

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