SRAM and its layout and access method
A static random access and memory technology, applied in static memory, digital memory information, information storage, etc., can solve problems such as poor performance of static random access memory, improve write noise tolerance, increase read noise tolerance, and improve stability Effect
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[0048] As mentioned in the background, the existing SRAM has poor performance. The (bit cell plane) layout of the existing SRAM is as follows figure 1 shown. It includes six transistors (none of which are labeled), figure 1 The floor plan shown shows the active regions (not labeled) and gates of six transistors. Usually SRAM includes a first drive transistor, a first load transistor, a second drive transistor and a second load transistor, by figure 1 It can be seen that the SRAM is located in the area surrounded by the rectangular dotted frame.
[0049] It should be noted that, for clarity of labeling, in each drawing of this specification, when labeling each gate, the lead wire is led out from one of the positions of the gate layer. However, those skilled in the art should understand that the gate layers above different active regions are different gates, that is, each gate is actually a part of the gate layer. For example figure 1 Among them, the gate D11 and the gate ...
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