memory array

Abstract

The present invention discloses a memory array. The memory array comprises a plurality of basic cell arrays, a word line set and a bit line set, wherein each basic cell array comprises 2*2 memory cell pairs; the word line set comprises a word line WL<m>, a first control grid line CG0<m> and a second control grid line CG1<m>; the bit line set comprises a bit line BL<3k>, a bit line BL<3k+1> and a bit line BL<3k+2>; the plurality of basic cell arrays are sequentially cascaded in column and row directions by the bit line set and the word line set; and each column of basic cell arrays is not associated with other columns. According to the memory array disclosed by the present invention, each group of memory cells is not associated with other groups of memory cells in the column direction, and thus, in a reading-out process, only a current of the group of memory cells needs to be processed; and the memory array is simple to decode and is suitable for development of a Native card.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a memory array. Background technique [0002] Since the Native card (small-value payment local card) has the advantages of fast application execution speed and high security, it has high requirements for chip resources. Flash memory is a storage body necessary for the normal operation of the system COS on the Native card. [0003] As a type of semiconductor memory, flash memory includes a memory array and peripheral circuits. figure 1 Is a schematic diagram of the structure of a memory array in the prior art, figure 2 It is a circuit diagram of a memory array in the prior art. Such as figure 1 and figure 2 As shown, the bit line BL in the column direction (Y direction) <0> , BL <1> , BL <2> , BL <3> Route for the second metal layer M2, row direction (X direction) CG0 <m> , WL <m> , CG1 <m> , CG0 <m+1> , WL <m+1> , CG...

AI Technical Summary

Problems solved by technology

[0008] Traditional flash storage cells are compactly arranged, which is convenient for designing large-capacity memory, but a virtual ground structure is required; and each column of flash memory with this virtual ground structure is related to at least two columns, and even the leakage of other columns has an impact on the read current. There are more factors to be considered in decoding, and the decoding circuit is therefore more complicated, which is not suitable for the development of Native cards that do not require large-capacity storage.

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