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High Speed ​​Data Interface Host Side Controller

A high-speed data interface, host-side technology, applied in electrical digital data processing, instruments, etc., can solve problems such as data jitter and affecting high-speed data transmission

Active Publication Date: 2018-04-03
VIA ALLIANCE SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] High-speed data interfaces, such as: Serial Advanced Technology Attachment (SATA), Peripheral Interconnect Express (PCIE), Secure Digital Input / Output Card (SDIO), Universal Serial Bus (USB), etc., are easily delayed by clock signals , and data jitter occurs; obviously affects high-speed data transmission

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  • High Speed ​​Data Interface Host Side Controller
  • High Speed ​​Data Interface Host Side Controller
  • High Speed ​​Data Interface Host Side Controller

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Embodiment Construction

[0011] The following description lists various embodiments of the present invention. The following description introduces the basic concept of the present invention and is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the claims.

[0012] figure 1 It is a block diagram describing a high-speed data interface host controller 100 implemented according to an embodiment of the present invention. The high-speed data interface host-side controller 100 includes a logical physical layer LPHY (the number is the same as the logical physical layer (logical physical layer) abbreviated LPHY), a plurality of electronic physical layers (electrical physical layer, abbreviated EPHY) EPHYA and EPHYB, a multiplexer ECLKMUX, and Cross-time domain data transmission module TXCDC. figure 1 Only two electronic physical layers are shown in , but the present invention is not limited thereto.

[0013] The electronic ...

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Abstract

The invention provides a host controller with low data jitter. According to the host controller, low speed data are provided by a logic physical layer, are sent to an electronic physical layer through a cross-time-domain data transmission module to be converted to high speed data by the electronic physical layer and are transmitted to an external device. Clock signals for operation of the electronic physical layer are further transmitted to the logic physical layer, so that the logic physical layer provides first low speed data according to the clock signals; the cross-time-domain data transmission module reads the low speed data provided by the logic physical layer for the external device according to a logic physical layer end clock and outputs the first low speed data to the electronic physical layer according to an electronic physical layer end clock.

Description

technical field [0001] The invention relates to a high-speed data interface host controller, in particular to a high-speed data interface host controller for high-speed transmission with external devices. Background technique [0002] High-speed data interfaces, such as: Serial Advanced Technology Attachment (SATA), Peripheral Interconnect Express (PCIE), Secure Digital Input / Output Card (SDIO), Universal Serial Bus (USB), etc., are easily delayed by clock signals , and data jitter occurs; it obviously affects high-speed data transmission. Contents of the invention [0003] The present invention provides a low data jitter host controller (host controller), which can also be realized by the south bridge of the chipset. [0004] A high-speed data interface host controller implemented according to an embodiment of the present invention includes a logical physical layer, an electronic physical layer, and a cross-time domain data transmission module. The logical physical laye...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38
CPCG06F13/385G06F2213/3802
Inventor 王万丰冀晓亮惠志强侯慧瑛
Owner VIA ALLIANCE SEMICON CO LTD