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FPGA configuration file loading method and decoder

A configuration file and decoder technology, which is applied in the direction of program loading/starting, code conversion, electrical components, etc., can solve the problems of long configuration files, slow configuration file loading speed, and slow FPGA chip configuration speed, etc.

Active Publication Date: 2019-04-09
CAPITAL MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to solve the problems in the prior art that it takes a long time to transmit the configuration file when the FPGA configuration file is loaded, the loading rate of the configuration file is slow, and the configuration speed of the FPGA chip is slow

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  • FPGA configuration file loading method and decoder
  • FPGA configuration file loading method and decoder
  • FPGA configuration file loading method and decoder

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Embodiment Construction

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0026] In order to facilitate the understanding of the embodiments of the present invention, further explanations will be given below with specific embodiments in conjunction with the accompanying drawings, which are not intended to limit the embodiments of the present invention.

[0027] figure 1 It is a flow chart of the FPGA configuration...

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Abstract

The invention relates to an FPGA configuration file loading method and a decoder. The method comprises the steps of receiving a compression instruction sent by a processor; dividing a first configuration file generated by performing RTL coding, synthesis as well as locating and wiring by adopting an EDA tool into a plurality of sub-files, obtaining same values and same value lengths of same sub-files and adding identifiers when at least two same sub-files exist in the sub-files, and compressing the first configuration file to generate a second configuration file; and loading the second configuration file to an FPGA chip and decompressing the second configuration file by utilizing the decoder to reduce the second configuration file into the first configuration file.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design in the field of microelectronics, in particular to a field programmable logic gate array (Field Programmable Gate Array, FPGA) configuration file loading method and a decoder. Background technique [0002] When loading the FPGA configuration file in the prior art, when the capacity of the configuration file is large, it often takes a long time to transmit the configuration file, resulting in a slow loading rate of the configuration file, which affects the configuration of the FPGA chip. speed. Contents of the invention [0003] The purpose of the present invention is to solve the problem in the prior art that it takes a long time to transmit the configuration file when the FPGA configuration file is loaded, the loading rate of the configuration file is slow, and the configuration speed of the FPGA chip is slow. [0004] First aspect, the embodiment of the present invention pro...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/445H03M7/30
Inventor 何轲乐毅军王宏宇
Owner CAPITAL MICROELECTRONICS
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