Method and system for quickly verifying addresses of large-scale interconnect chips based on BFM

Abstract

The embodiment of the invention discloses a BFM-based method and system for rapidly verifying an address of a large-sized inter-connected chip. The method comprises the following steps of sending a writing instruction to a target chip by a forwarding chip, wherein the writing instruction comprises target address information and verification data; receiving feedback information sent by the forwarding chip after the verification data is written into a target address by the target chip; and sending a reading instruction to the target chip by the forwarding chip, receiving the verification data read from the target address through the target chip by the forwarding chip, judging whether the verification data written into the target address is consistent with the verification data read from the target address or not, if yes, the target address is successfully verified. Therefore, in the embodiment, the verification correctness is ensured through address verification of first writing and then reading, a verification code is simple and short and is high in readability, the verification speed is greatly increased, and the production period of the chip is shortened.

Description

technical field [0001] The invention relates to the technical field of chip address reading and writing, and more specifically relates to a method and system for rapidly verifying addresses of large-scale interconnected chips based on BFM. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the development cycle of chips is gradually shortened, and the earlier products with the same function are launched, the greater their competitiveness. The time required for verification work becomes a bottleneck restricting the product development cycle. Due to the large scale of large-scale interconnection chip NC, it is not suitable for large-scale module-level verification, so the combination of BFM model for system-level simulation verification has become a necessary verification method for verifying large-scale interconnection chip NC. The verification of large-scale interconnection chip NC is a tedious and time-consuming task. I...

AI Technical Summary

Problems solved by technology

The verification of large-scale interconnection chip NC is a tedious and time-consuming task. In order to improve the verification efficiency of integrated circuits and shorten the product cycle, the verification personnel must shorten the verification cycle as much as possible on the premise of ensuring that the chip verification is correct.

Images