Load balancing method and device based on output state feedback in CLOS system

A technology of output status and load balancing, applied in transmission systems, digital transmission systems, electrical components, etc.

Active Publication Date: 2016-06-01
FENGHUO COMM SCI & TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] Aiming at the defects in the prior art, the technical problem to be solved by the present invention is: to effectively realize load balancing in the CLOS system, so that the working efficiency and performance of the system will not decrease due to burst or unbalanced load, thereby maintaining the system Overall Scheduling Capabilities and Performance

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  • Load balancing method and device based on output state feedback in CLOS system
  • Load balancing method and device based on output state feedback in CLOS system
  • Load balancing method and device based on output state feedback in CLOS system

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Embodiment Construction

[0065] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0066] see figure 2 As shown, the embodiment of the present invention provides a load balancing method based on output state feedback in a CLOS system. The CLOS system includes several input modules IM, several intermediate modules CM and several output modules OM, and each CM is connected to Each IM is connected to each OM, and the load balancing method includes the following steps:

[0067] Step S1: Store the cache status information of each CM in the corresponding data cell; periodically send the data cell to each OM in multiple rounds of sending, that is, in each round of sending, all CMs correspond to The data cells are sent to one OM in turn, starting from the first OM, sending multiple rounds, and then turning to step S2.

[0068] Each link of the egress cache of the CM is independent. In this embodiment, the cache states of...

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Abstract

The invention discloses a load balancing method and device based on output state feedback in a CLOS system, and relates to the technical field of load balancing of the CLOS system. The method comprises the following steps that: cache state information of CMs (Central Modules) is stored in corresponding data cells, and the corresponding data cells are transmitted to OMs (Output Modules); after the data cells are received, the OMs resolve cache states of the CMs, and transmit the resolved cache states to IMs (Input Modules); the IMs build CM cache state lists according to the cache states transmitted by the OMs, and update the built CM cache state lists; and the IMs obtain bit vector groups feeding back cache state minimum values with the CM cache state lists in a mode based on output state feedback, perform calculation and inquiry according to the bit vector groups to obtain links of data cells to be transmitted, and transmit the data cells to be transmitted through the links under the condition that the links are valid. Through adoption of the load balancing method and device, the working efficiency and performance of the CLOS system are not lowered due to load unbalance, so that the overall scheduling capability and performance of the system are maintained.

Description

technical field [0001] The invention relates to the technical field of load balancing of a CLOS (Clos Exchange Architecture) system, in particular to a load balancing method and device based on output state feedback in the CLOS system. Background technique [0002] The CLOS system based on cells (CELL) has the characteristics of non-blocking, expandable and large capacity, and has become the mainstream of switching chips at present. Such as figure 1 As shown, the traditional CLOS system includes several IMs (input modules), several CMs (intermediate modules) and several OMs (output modules), which can form a 3-level CLOS structure and can be easily expanded to 5 levels CLOS structure. By folding, IM and OM functions can be implemented in one chip, while CM can be implemented in another chip. [0003] Ethernet data packets are variable in length, and the maximum packet length may reach 16,000 bytes. Switching based on data packets in the switch chip will bring a large dela...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/803H04L12/933H04L12/937H04L12/947
CPCH04L47/125H04L49/1515H04L49/25H04L49/254
Inventor 屈琴书
Owner FENGHUO COMM SCI & TECH CO LTD
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