Semiconductor chip packaging structure and packaging method thereof

Abstract

The invention provides a semiconductor chip packaging structure and a packaging method thereof. The semiconductor chip packaging structure comprises a semiconductor chip, a protection substrate and a supporting structure, wherein one surface of the semiconductor chip is provided with a functional area; the protection substrate covers the surface, provided with the functional area, of the semiconductor chip; the supporting structure is located between the semiconductor chip and the protection substrate and comprises multiple supporting arms connected end to end, the supporting arms, the semiconductor chip and the protection substrate define a sealed cavity, and the functional area is located in the sealed cavity; at least one supporting arm is provided with at least one supporting protrusion extending towards the functional area. Through arrangement of the supporting protrusions, steam can generate a vortex in the corner areas of the supporting protrusions, the vortex and the steam collide with and rub at each other to generate energy losses, the impact force of the steam on the supporting structure is reduced, and therefore the problem of layered cracking of the supporting structure is effectively solved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to the packaging technology of semiconductor chips. Background technique [0002] Wafer Level Chip Size Packaging (WLCSP) is a technology that packages the entire wafer and then cuts it to obtain a single finished chip. Wafer-level chip-scale packaging technology complies with the market's increasingly light, small, short, thin and low-cost requirements for microelectronic products. The size of the chip after dicing is almost the same as the size of the die, and the packaging cost is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technology is a hot spot in the current packaging field and a future development trend. A single finished chip obtained by packaging and cutting needs to be tested for reliability, and only finished chips that pass the reliability test can be identified as qualified chi...

AI Technical Summary

Problems solved by technology

[0004] However, in the reliability test, the support structure 101 may appear delamination and cracking, which affects the quality of the finished chip, and becomes a problem to be solved by those skilled in the art.

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